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add effect mixer module and posibility to switch effects

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Imants Pulkstenis
2019-11-24 21:59:44 +02:00
parent 518bbe43cb
commit 11c36aec2d
6 changed files with 315 additions and 34 deletions
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clipping.v
+2 -2
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@@ -13,11 +13,11 @@ module clipping_effect #( parameter
); );
//-------------Internal Constants--------------------------- //-------------Internal Constants---------------------------
localparam [3:0] IDLE = 'd0, localparam [2:0] IDLE = 'd0,
CLIP = 'd1, CLIP = 'd1,
OUTPUT = 'd2; OUTPUT = 'd2;
reg [3:0] r_state=IDLE, r_next=IDLE; reg [2:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0; reg signed [data_width-1: 0] r_data = 'b0;
reg signed [data_width-1: 0] r_treshhold_p = 'b0; reg signed [data_width-1: 0] r_treshhold_p = 'b0;
effect_controler.v
+37 -4
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@@ -12,10 +12,18 @@ module effect_controler #( parameter
output signed [d_width-1: 0] o_l_data, output signed [d_width-1: 0] o_l_data,
output signed [d_width-1: 0] o_r_data, output signed [d_width-1: 0] o_r_data,
output o_read_done, // read done from effects module
output o_read_ready, // ready read from reefects module
input [1:0] sw, // effect control swiches
output signed [memory_d_width-1: 0] o_data_to_eff, // Data output to effects module output signed [memory_d_width-1: 0] o_data_to_eff, // Data output to effects module
output o_data_valid, // data valid to read (FIFO not empty). data valid signal to effect module output o_data_valid, // data valid to read (FIFO not empty). data valid signal to effect module
input i_read_enable, input i_read_enable, // enable read from input fifo
input signed [memory_d_width-1: 0] i_data_from_eff, // Data output to effects module input signed [memory_d_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
input signed [memory_d_width-1: 0] i_data_from_eff_sw1, // Data output to effects module
input i_dv_from_eff // data valid to read (FIFO not empty). data valid signal to effect module input i_dv_from_eff // data valid to read (FIFO not empty). data valid signal to effect module
); );
@@ -26,9 +34,14 @@ wire signed [memory_d_width-1: 0] w_o_data; //output data to io_module
wire w_empty_in, w_full_in; wire w_empty_in, w_full_in;
wire w_empty_out, w_full_out; wire w_empty_out, w_full_out;
wire [memory_d_width-1:0] w_data_to_fifo; // wire connets mixer to output fifo
wire [address_width-1:0] w_data_fill_input; // shows how full are in FIFO memmory for intput wire [address_width-1:0] w_data_fill_input; // shows how full are in FIFO memmory for intput
wire [address_width-1:0] w_data_fill_output; // shows how full are in FIFO memmory for output wire [address_width-1:0] w_data_fill_output; // shows how full are in FIFO memmory for output
wire w_data_valid_to_fifo; // data valid to write output FIFO from mixer
assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
@@ -62,14 +75,34 @@ sync_fifo #(
.full(w_full_out), .full(w_full_out),
.empty(w_empty_out), .empty(w_empty_out),
.data_fill(w_data_fill), .data_fill(w_data_fill),
.data_in(i_data_from_eff), .data_in(w_data_to_fifo),
.w_clk(clk), .w_clk(clk),
.r_clk(mclk), .r_clk(mclk),
.reset(reset), .reset(reset),
.wr_en( w_full_out ? 1'b0 : i_dv_from_eff ), // checking is FIFO full .wr_en( w_data_valid_to_fifo ), // checking of FIFO full are performing mixer module
.rd_en( w_empty_out ? 1'b0 : 1'b1 ) // checking is FIFO empty .rd_en( w_empty_out ? 1'b0 : 1'b1 ) // checking is FIFO empty
); );
// Effect mixer, performs audio data merging
effect_mixer #(
.data_width(memory_d_width) // memory data width
) effect_mixer (
.sw(sw),
.clk(clk),
.reset(reset),
.i_fifo_full(w_full_out),
.o_read_done(o_read_done), // read from effect module done
.o_read_ready(o_read_ready), // ready to read from effect module
.o_data(w_data_to_fifo), // data to output FIFO memory
.o_data_valid(w_data_valid_to_fifo),
.i_dv_from_eff(i_dv_from_eff),
.i_data_from_eff_sw0(i_data_from_eff_sw0), // Data output to effects module
.i_data_from_eff_sw1(i_data_from_eff_sw1)
);
endmodule endmodule
effect_mixer.v
+129
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@@ -0,0 +1,129 @@
module effect_mixer #( parameter
data_width = 16 // data width
)(
input clk,
input [1:0] sw,
input reset,
input i_fifo_full,
output signed [data_width-1: 0] o_data,
output o_read_done, // read from effect module done
output o_read_ready, // ready to read from effect module
output o_data_valid, // data valit to write in FIFO memory
input i_dv_from_eff,
input signed [data_width-1: 0] i_data_from_eff_sw0, // Data output to effects module
input signed [data_width-1: 0] i_data_from_eff_sw1
);
//-------------Internal Constants---------------------------
localparam [2:0] IDLE = 'd0,
ADD = 'd1,
NORM = 'd2,
OUTPUT = 'd3;
reg [2:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data_sw0 = 'b0;
reg signed [data_width-1: 0] r_data_sw1 = 'b0;
reg signed [data_width: 0] r_data_add = 'b0;
reg signed [data_width-1: 0] r_data_norm = 'b0;
reg r_read_done = 0;
reg r_read_ready = 0;
reg r_data_valid = 0;
assign o_read_done = r_read_done;
assign o_data_valid = r_data_valid;
assign o_data = r_data_norm;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (reset == 1) begin
// clear state
r_state <= IDLE;
r_next <= IDLE;
end
else begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
case(r_state)
IDLE : begin
if (i_dv_from_eff == 1) begin
r_next <= ADD;
r_data_sw0 <= i_data_from_eff_sw0;
r_data_sw1 <= i_data_from_eff_sw1;
r_read_done <= 1;
r_read_ready <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_ready <= 1; // redy to read data
r_data_valid <= 0;
end
end
ADD : begin
case ( sw )
0 : begin // off all sound
r_data_add <= 0;
end
1 : begin // no effect only
r_data_add <= r_data_sw0;
end
2 : begin // clipping effect only
r_data_add <= r_data_sw1;
end
3 : begin // no effect and clipping effect
r_data_add <= r_data_sw0 + r_data_sw1;
end
endcase
r_next <= NORM;
r_read_done <= 0;
end
NORM : begin
case ( sw )
0 : begin // off all sound
r_data_norm <= 0;
end
1 : begin // no effect only
r_data_norm <= r_data_add[data_width-1: 0];
end
2 : begin // clipping effect only
r_data_norm <= r_data_add[data_width-1: 0];
end
3 : begin // no effect and clipping effect
r_data_norm <= r_data_add[data_width-1: 0] >>> 1; // Shift Right, Arithmetic (keep sign)
end
endcase
r_next <= OUTPUT;
end
OUTPUT : begin
if ((i_fifo_full == 1) & (i_dv_from_eff == 1)) begin // wait for FIFO memory and data valid in effect module
r_next <= OUTPUT;
r_read_done <= 0;
r_read_ready <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_ready <= 0; // redy to read data
r_data_valid <= 1; // data valid to write in FIFO
end
end
default: r_next <= IDLE; // on error
endcase
end
endmodule
effect_module.v
+50 -21
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@@ -6,37 +6,66 @@ module effect_module #( parameter
input [1:0] sw, // effect control swiches input [1:0] sw, // effect control swiches
input i_data_ready, // data ready to read input i_data_ready, // data ready to read
input signed [d_width-1: 0] i_data, // data input form effect controler input signed [d_width-1: 0] i_data, // data input form effect controler
output o_read_enable, // enable data reading
input i_read_done, // read done from effects controler input i_read_done, // read done from effects controler
output signed [d_width-1: 0] o_data, // data output form effect controler
output o_data_valid output o_data_valid,
output o_read_enable,
// SW0 no effect
output signed [d_width-1: 0] o_data_sw0, // data output form effect controler
// SW1 clipping effect
output signed [d_width-1: 0] o_data_sw1 // data output form effect controler
); );
// Wires for cliping effect // Wires for cliping effect
wire signed [d_width-1: 0] w_data_ce; wire signed [d_width-1: 0] w_data_sw0;
wire w_read_enable_ce; wire w_read_enable_sw0;
wire w_data_valid_ce; wire w_data_valid_sw0;
wire signed [d_width-1: 0] w_data_sw1;
wire w_read_enable_sw1;
wire w_data_valid_sw1;
// asynchronous logic ---------------------------------------
assign o_data_sw0 = w_data_sw0;
assign o_data_sw1 = w_data_sw1;
assign o_read_enable = w_read_enable_sw0 & w_read_enable_sw1;
assign o_data_valid = w_data_valid_sw0 & w_data_valid_sw1;
// Individual effect modules -----------------------------
// no effect SW0
no_effect #(
.data_width(d_width) // data width
) no_effect (
.clk(clk),
.reset(reset),
.i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready),
.o_data(w_data_sw0),
.o_read_enable(w_read_enable_sw0),
.o_data_valid(w_data_valid_sw0)
);
assign o_data = w_data_ce;// ? w_data_ce : 'b0 ;
assign o_read_enable = w_read_enable_ce;//(i_data_ready & w_data_valid_ce ) ? w_read_enable_ce : 0 ;
assign o_data_valid = w_data_valid_ce;//(i_data_ready & w_data_valid_ce ) ? w_data_valid_ce : 0 ;
// clipping effect SW1
// clipping effect
clipping_effect #( clipping_effect #(
.data_width(d_width) // data width .data_width(d_width) // data width
) clipping_effect ( ) clipping_effect (
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.i_treshhold(16'h00f0), .i_treshhold(16'h00f0),
.i_data(i_data), .i_data(i_data),
.i_read_done(i_data_ready), .i_read_done(i_read_done), // read done from effects controler
.o_data(w_data_ce), .i_data_ready(i_data_ready),
.o_read_enable(w_read_enable_ce), .o_data(w_data_sw1),
.o_data_valid(w_data_valid_ce), .o_read_enable(w_read_enable_sw1),
.i_data_ready(i_data_ready) .o_data_valid(w_data_valid_sw1)
); );
no_effect.v
+77
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@@ -0,0 +1,77 @@
module no_effect #( parameter
data_width = 16 // data width
)(
input clk,
input reset,
input signed [data_width-1: 0] i_data,
output signed [data_width-1: 0] o_data,
input i_read_done,
output o_read_enable,
output o_data_valid,
input i_data_ready
);
//-------------Internal Constants---------------------------
localparam [3:0] IDLE = 'd0,
OUTPUT = 'd1;
reg [3:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0;
reg r_read_enable = 0;
reg r_data_valid = 0;
assign o_read_enable = r_read_enable;
assign o_data_valid = r_data_valid;
assign o_data = r_data;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (reset == 1) begin
// clear state
r_state <= IDLE;
r_next <= IDLE;
end
else begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
case(r_state)
IDLE : begin
if (i_data_ready == 1) begin
r_next <= OUTPUT;
r_data <= i_data;
r_read_enable <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_enable <= 1; // redy to read data
r_data_valid <= 0;
end
end
OUTPUT : begin
if (i_read_done == 1) begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
else begin
r_next <= OUTPUT;
r_data_valid <= 1;
r_read_enable <= 0; // read disable
end
end
default: r_next <= IDLE; // on error
endcase
end
endmodule
top.v
+20 -7
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@@ -35,21 +35,28 @@ wire clk_25MHz; //
wire w_reset, w_reset1, w_reset2, w_reset3, wire w_reset, w_reset1, w_reset2, w_reset3,
w_reset4, w_reset5; w_reset4, w_reset5;
wire w_internal_reset;
wire [d_width-1: 0] r_data_tx; wire [d_width-1: 0] r_data_tx;
wire [d_width-1: 0] l_data_tx; wire [d_width-1: 0] l_data_tx;
wire [d_width-1: 0] r_data_rx; wire [d_width-1: 0] r_data_rx;
wire [d_width-1: 0] l_data_rx; wire [d_width-1: 0] l_data_rx;
wire [d_width-1: 0] w_data_to_eff; wire [d_width-1: 0] w_data_to_eff;
wire w_dv_to_eff; wire w_dv_to_eff;
wire [d_width-1: 0] w_data_from_eff;
wire w_dv_from_eff; wire w_dv_from_eff;
wire w_rd_en_from_eff; wire w_rd_en_from_eff;
wire w_internal_reset; wire w_read_done_eff; // read done from effects module to mixer
wire w_read_ready_eff; // ready to read from effects module
// Data wires from effects module to effect controler
wire [d_width-1: 0] w_data_from_eff_sw0;
wire [d_width-1: 0] w_data_from_eff_sw1;
//-----sub modules-------------------------- //-----sub modules--------------------------
@@ -129,18 +136,22 @@ effect_controler #(
) effect_controler ( ) effect_controler (
.reset(w_reset), // asynchronous active high reset .reset(w_reset), // asynchronous active high reset
.mclk(master_clk), .mclk(master_clk),
.sw(sw),
.clk(clk_25MHz), .clk(clk_25MHz),
.i_l_data(l_data_rx), // left channel data received .i_l_data(l_data_rx), // left channel data received
.i_r_data(r_data_rx), // right channel data received .i_r_data(r_data_rx), // right channel data received
.o_l_data(l_data_tx), // left channel data to transmit .o_l_data(l_data_tx), // left channel data to transmit
.o_r_data(r_data_tx), // right channel data to transmit .o_r_data(r_data_tx), // right channel data to transmit
.o_read_done(w_read_done_eff), // read done from effects controler
.o_read_ready(w_read_ready_eff), // ready read from reefects module
.o_data_to_eff(w_data_to_eff), // Data output to effects module .o_data_to_eff(w_data_to_eff), // Data output to effects module
.o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module .o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module
.i_read_enable(w_rd_en_from_eff), // read enable from Effect module .i_read_enable(w_rd_en_from_eff), // read enable from Effect module
.i_data_from_eff(w_data_from_eff), // Data input from effects module .i_dv_from_eff(w_dv_from_eff), // data valid write (FIFO not full). data valid signal from effect module
.i_dv_from_eff(w_dv_from_eff) // data valid write (FIFO not full). data valid signal from effect module .i_data_from_eff_sw0(w_data_from_eff_sw0), // Data input from effects module
.i_data_from_eff_sw1(w_data_from_eff_sw1) // Data input from effects module
); );
@@ -152,10 +163,12 @@ effect_module #(
.reset(w_reset), .reset(w_reset),
.sw(sw), // effect control swiches .sw(sw), // effect control swiches
.i_data_ready(w_dv_to_eff), // data ready to read .i_data_ready(w_dv_to_eff), // data ready to read
.i_read_done(w_read_done_eff), // read done from effects controler
.i_data(w_data_to_eff), // data input form effect controler .i_data(w_data_to_eff), // data input form effect controler
.o_read_enable(w_rd_en_from_eff), // enable data reading .o_read_enable(w_rd_en_from_eff), // enable data reading
.o_data(w_data_from_eff), .o_data_valid(w_dv_from_eff),
.o_data_valid(w_dv_from_eff) .o_data_sw0(w_data_from_eff_sw0),
.o_data_sw1(w_data_from_eff_sw1)
); );