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fifo module now working in loopback mode

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Imants Pulkstenis
2019-11-21 23:01:00 +02:00
parent b8bfb00389
commit 07cfe9893d
3 changed files with 15 additions and 15 deletions
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blockram.v
+4 -4
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@@ -7,16 +7,16 @@
// Dual-Port Block RAM with Two Write Ports
// File: blobkram.v
module ram #( parameter
module blockram #( parameter
DEPTH = 16,
ADDR_WIDTH = 4,
DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
input clka,clkb,ena,enb,wea,web;
input [ADDR_WIDTH-1:0] addra,addrb;
input [DATA_WIDTH-1:0] dia,dib;
output [DATA_WIDTH-1:0] doa,dob;
reg [ADDR_WIDTH-1:0] ram [ DEPTH - 1 :0];
input signed [DATA_WIDTH-1:0] dia,dib;
output signed [DATA_WIDTH-1:0] doa,dob;
reg [DATA_WIDTH-1:0] ram [ DEPTH - 1 :0];
reg [DATA_WIDTH-1:0] doa,dob;
always @(posedge clka)