37 lines
913 B
Verilog
37 lines
913 B
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 29.03.2020
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// Project name - PS04
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// Module name - DDS (direct digital synthesis)
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//
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// Detailed module description:
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// Aim of this problem set – to practice Direct Digital Synthesis in FPGA
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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// define connections to outside
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module dds_vhdl#( parameter
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phase_width = 4,
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data_width = 8
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)(
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input clk, //100mhz clock
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input rst, //rst
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input [1:0] control,
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input [phase_width - 1:0] phase_incr, //"frequency"
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output [phase_width - 1:0] phase_out,
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output [data_width - 1:0] signal_out);
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// define inside of the module
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lookuptable lookuptable (
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.in(),
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.out());
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endmodule |