86 lines
1.7 KiB
VHDL
86 lines
1.7 KiB
VHDL
-----------------------------
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-- Author Imants Pulkstenis
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-- Date 10.06.2020
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-- Project name Labwork No3
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-- Module name lab3_tb
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--
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-- Detailed module description
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-- Test bench for top module of lab.No.3
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--
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity lab3_tb is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16
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);
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end lab3_tb;
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--define inside of the module
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architecture behavioral of lab3_tb is
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--signals
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signal clk : std_logic := '0'; --100mhz clock
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signal rst : std_logic := '0'; --rst
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component lab3 is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic --rst
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);
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end component;
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constant clk_period : time := 10 ns;
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begin
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clk <= not clk after clk_period/2;
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uut : lab3
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generic map
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(
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phase_width => phase_width,
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data_width => data_width
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)
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port map
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(
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clk => clk,
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rst => rst
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);
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--tb process
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process
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begin
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rst <= '1';
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wait for 100 ns;
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rst <= '0';
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-- wait for clk_period/2;
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wait;
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end process;
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end behavioral; |