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bcfcc84975c31be021e2c1ec2b201b6c7275c1d3
RTR532/ld3/dds_vhdl
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Imants Pulkstenis bcfcc84975 Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
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fir
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir_sim
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir_import_coef.txt
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir_sim.f
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.bsf
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.cmp
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.qip
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.sip
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.spd
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
fir.vhd
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
IIR.vhd
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
lab3_tb.vhd
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
lab3.vhd
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
sin_gen_sum_tb.vhd
Signal sum and signal sum test bench now working.
2020-06-09 14:40:44 +03:00
sin_gen_sum.vhd
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
sin_gen_tb.vhd
Added clock divider 22050Hz. Tested!
2020-06-09 00:04:30 +03:00
sin_gen.qpf
Added clock divider 22050Hz. Tested!
2020-06-09 00:04:30 +03:00
sin_gen.qsf
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00
sin_gen.qws
Add files for FIR and IIR filter - not tested
2020-06-09 22:28:53 +03:00
sin_gen.vhd
Still need to work on FIR, but IIR is working.
2020-06-10 01:30:00 +03:00