193 lines
7.2 KiB
VHDL
193 lines
7.2 KiB
VHDL
-----------------------------
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-- Author Imants Pulkstenis
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-- Date 09.06.2020
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-- Project name Labwork No3
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-- Module name lab3
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--
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-- Detailed module description
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-- Top level module for Lab.No3
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-- The top module contains two signal generator modules,
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-- a signal sum module, and two filters. The first filter
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-- is generated using Altera Megawizard plugin IP Core,
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-- but second, using the Simulink HDL code generator.
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--
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity lab3 is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16;
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phase_incr_one : integer := 37; -- 22050/1664
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phase_incr_two : integer := 57;
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sampling_f : integer := 4535; -- 100MHz/22050
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clock_cnt_width : integer := 13
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic --rst
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);
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end lab3;
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--define inside of the module
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architecture behavioral of lab3 is
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--define inside use signals
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signal signal_f_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
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signal signal_f_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
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signal signal_sum : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
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signal clk_22050 : std_Logic := '0';
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--define components to use
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component sin_gen is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16;
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sampling_f : integer := 4535; -- 100MHz/22050Hz
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clock_cnt_width : integer := 13
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic; --rst
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phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
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phase_out : out std_Logic_vector(phase_width - 1 downto 0);
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signal_out : out std_Logic_vector(data_width - 1 downto 0);
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fs_out : out std_logic --output sampling clock 22050Hz
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);
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end component;
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component sin_gen_sum is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16
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);
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port
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(
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clk : in std_logic; --100mhz clock
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--rst : in std_logic; --rst
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signal_in_one : in std_Logic_vector(data_width - 1 downto 0);
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signal_in_two : in std_Logic_vector(data_width - 1 downto 0);
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signal_out : out std_Logic_vector(data_width - 1 downto 0)
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);
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end component;
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component IIR is
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port( clk : IN std_logic;
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reset : IN std_logic;
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clk_enable : IN std_logic;
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In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
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ce_out : OUT std_logic;
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Out1 : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
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);
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end component;
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component fir is
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port (
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clk : in std_logic := '0'; -- clk.clk
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reset_n : in std_logic := '0'; -- rst.reset_n
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ast_sink_data : in std_logic_vector(15 downto 0) := (others => '0'); -- avalon_streaming_sink.data
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ast_sink_valid : in std_logic := '0'; -- .valid
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ast_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error
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ast_source_data : out std_logic_vector(36 downto 0); -- avalon_streaming_source.data
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ast_source_valid : out std_logic; -- .valid
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ast_source_error : out std_logic_vector(1 downto 0) -- .error
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);
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end component;
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begin --define the operation of the module!
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sin_gen_one : sin_gen -- first signal generator
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generic map
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(
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phase_width => phase_width,
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data_width => data_width,
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sampling_f => sampling_f,
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clock_cnt_width => clock_cnt_width
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)
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port map
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(
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clk => clk,
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rst => rst,
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phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
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--phase_out => phase_out,
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signal_out => signal_f_one,
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fs_out => clk_22050
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);
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sin_gen_two : sin_gen -- second signal generator
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generic map
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(
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phase_width => phase_width,
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data_width => data_width,
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sampling_f => sampling_f,
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clock_cnt_width => clock_cnt_width
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)
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port map
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(
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clk => clk,
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rst => rst,
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phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
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--phase_out => phase_out,
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signal_out => signal_f_two
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);
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sin_gen_sum_one : sin_gen_sum -- signal sumator
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generic map
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(
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phase_width => phase_width,
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data_width => data_width
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)
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port map
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(
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clk => clk,
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--rst => rst,
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signal_in_one => signal_f_one,
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signal_in_two => signal_f_two,
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signal_out => signal_sum
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);
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iir_one : IIR -- IIR filter from Simulink
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port map
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(
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clk => clk_22050,
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reset => rst,
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clk_enable => '1',
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In1 => signal_sum--, -- sfix16_En14
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--ce_out =>,
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--Out1 => -- sfix16_En14
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);
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fir_one : fir -- FIR filter from Altera Megawizard plugin IP Core
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port map
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(
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clk => clk, -- clk.clk
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reset_n => rst, -- rst.reset_n
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ast_sink_data => signal_sum,-- avalon_streaming_sink.data
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ast_sink_valid => '1', -- .valid
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ast_sink_error => "00" -- .error
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-- ast_source_data => -- avalon_streaming_source.data
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-- ast_source_valid => -- .valid
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-- ast_source_error => -- .error
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);
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end behavioral; |