106 lines
2.0 KiB
VHDL
106 lines
2.0 KiB
VHDL
-----------------------------
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-- Author -
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-- Date -
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-- Project name -
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-- Module name -
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--
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-- Detailed module description
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity dds_vhdl is
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generic
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(
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phase_width : integer := 4;
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data_width : integer := 8
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic; --rst
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phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
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phase_out : out std_Logic_vector(phase_width - 1 downto 0);
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signal_out : out std_Logic_vector(data_width - 1 downto 0)
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);
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end dds_vhdl;
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--define inside of the module
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architecture behavioral of dds_vhdl is
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--define inside use signals
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type rom_table is array ( 0 to 2**phase_width - 1) of std_logic_vector(data_width - 1 downto 0);
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constant signal_rom_table : rom_table :=
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(
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0 => x"FF",
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1 => x"FF",
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2 => x"FF",
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3 => x"FF",
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4 => x"FF",
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5 => x"FF",
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6 => x"FF",
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7 => x"FF",
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8 => x"00",
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9 => x"00",
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10 => x"00",
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11 => x"00",
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12 => x"00",
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13 => x"00",
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14 => x"00",
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15 => x"00"
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);
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-- phase counter
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signal phase_cnt : unsigned(phase_width - 1 downto 0) := (others => '0');
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begin --define the operation of the module!
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--phase output for debugging
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phase_out <= std_logic_Vector(phase_cnt);
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--phase counter
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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phase_cnt <=
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else
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phase_cnt <=
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end if;
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end if;
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end process;
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--data output
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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signal_out <=
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else
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--assign value from table
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signal_out <=
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end if;
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end if;
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end process;
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end behavioral;
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