108 lines
2.4 KiB
VHDL
108 lines
2.4 KiB
VHDL
-----------------------------
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-- Author Imants Pulkstenis
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-- Date 08.06.2020
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-- Project name Labwork No3
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-- Module name sin_gen_tb
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--
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-- Detailed module description
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-- Test bench for signal generator
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--
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity sin_gen_tb is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16
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);
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end sin_gen_tb;
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--define inside of the module
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architecture behavioral of sin_gen_tb is
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--signals
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signal clk : std_logic := '0'; --100mhz clock
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signal rst : std_logic := '0'; --rst
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signal phase_incr : std_Logic_vector(phase_width - 1 downto 0) := (others => '0'); --"frequency"
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signal phase_out : std_Logic_vector(phase_width - 1 downto 0) := (others => '0');
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signal signal_out : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
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--signal fs_out : std_logic := '0';
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--define components to use
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component sin_gen is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic; --rst
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phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
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phase_out : out std_Logic_vector(phase_width - 1 downto 0);
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signal_out : out std_Logic_vector(data_width - 1 downto 0)--;
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--fs_out : in std_logic
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);
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end component;
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constant clk_period : time := 10 ns;
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begin
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clk <= not clk after clk_period/2;
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uut : sin_gen
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generic map
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(
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phase_width => phase_width,
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data_width => data_width
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)
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port map
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(
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clk => clk,
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rst => rst,
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phase_incr => phase_incr,
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phase_out => phase_out,
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signal_out => signal_out--,
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--fs_out => fs_out
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);
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--tb process
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process
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begin
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rst <= '1';
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wait for 100 ns;
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rst <= '0';
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wait for clk_period/2;
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--phase_incr <= (0 => '1', others => '0'); --1
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--phase_incr <= (5 => '1',2 => '1', 1=> '1', others => '0'); --37
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phase_incr <= (5 => '1',4 => '1',3 => '1', 0=> '1', others => '0'); --57
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wait;
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end process;
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end behavioral;
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