109 lines
3.1 KiB
VHDL
109 lines
3.1 KiB
VHDL
-----------------------------
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-- Author - Imants Pulkstenis
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-- Date - 08.06.2020
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-- Project name - Lab work No3
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-- Module name - sin_gen_sum
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--
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-- Detailed module description:
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-- This is top module containing
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-- signal genrators, FIR and IIR filter
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity sin_gen_sum is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16;
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phase_incr_one : integer := 37;
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phase_incr_two : integer := 57
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic; --rst
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--phase_incr_one : in std_Logic_vector(phase_width - 1 downto 0); --"frequency for first signal"
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--phase_incr_two : in std_Logic_vector(phase_width - 1 downto 0); --"frequency for second signal"
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signal_out : out std_Logic_vector(data_width - 1 downto 0)
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);
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end sin_gen_sum;
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--define inside of the module
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architecture behavioral of sin_gen_sum is
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--define inside use signals
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signal signal_out_one : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
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signal signal_out_two : std_Logic_vector(data_width - 1 downto 0) := (others => '0');
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signal signal_summ : std_Logic_vector(data_width downto 0) := (others => '0'); -- 17bit word
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--define components to use
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component sin_gen is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic; --rst
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phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
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--phase_out : out std_Logic_vector(phase_width - 1 downto 0);
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signal_out : out std_Logic_vector(data_width - 1 downto 0)
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);
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end component;
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begin --define the operation of the module!
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--signal output
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signal_out <= std_logic_Vector(signal_summ(data_width downto 1));
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sin_gen_one : sin_gen
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generic map
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(
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phase_width => phase_width,
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data_width => data_width
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)
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port map
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(
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clk => clk,
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rst => rst,
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phase_incr => std_logic_Vector(To_unsigned(phase_incr_one,phase_width)),
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--phase_out => phase_out,
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signal_out => signal_out_one
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);
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sin_gen_two : sin_gen
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generic map
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(
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phase_width => phase_width,
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data_width => data_width
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)
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port map
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(
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clk => clk,
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rst => rst,
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phase_incr => std_logic_Vector(To_unsigned(phase_incr_two,phase_width)),
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--phase_out => phase_out,
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signal_out => signal_out_two
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);
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--adder
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process(clk)
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begin
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if rising_edge(clk) then
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signal_summ <= signed(signal_out_one) + signed(signal_out_two);
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end if;
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end process;
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end behavioral; |