109 lines
2.6 KiB
VHDL
109 lines
2.6 KiB
VHDL
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-- Author - Kriss Osmanis
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-- Date - 2017-02-25; 2019-02-20
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-- Project name - PS02
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-- Module name - PS02 signal generator
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--
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-- Detailed module description
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-- generates values for A, B, op
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--
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--
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-- Revision:
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-- A - initial design
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-- B - modified op seq
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity ps02_siggen is
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generic
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(
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data_width : integer := 32
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);
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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A : out std_Logic_vector(data_width - 1 downto 0);
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B : out std_logic_vector(data_width - 1 downto 0);
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op : out std_logic_vector(3 downto 0)
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);
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end ps02_siggen;
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--define inside of the module
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architecture behavioral of ps02_siggen is
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--define inside use signals
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signal op_cnt : unsigned(3 downto 0) := x"0";
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type A_B_value_array is array (0 to 15) of std_logic_vector(data_width - 1 downto 0);
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signal A_list : A_B_value_array :=
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(
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std_logic_vector(to_signed(-15,data_width)), --sub
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std_logic_vector(to_signed(-14,data_width)), --add
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x"0000DEAD", --nand
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x"0000BEEF", --and
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x"0000ABCD", --or
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x"0000EFAD", --nor
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x"00001279", --xor
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x"00000310", --not a
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x"00003010", --not b
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std_logic_vector(to_signed(-1,data_width)),--incr B
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std_logic_vector(to_signed(0,data_width)),--incr A
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std_logic_vector(to_signed(0,data_width)),--sub A
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std_logic_vector(to_signed(0,data_width)),--sub B
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x"00000F0F",--sll A
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x"00000000",--sll B
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x"00001234"--noop
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);
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signal B_list : A_B_value_array :=
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(
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std_logic_vector(to_signed(37,data_width)), --sub
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std_logic_vector(to_signed(-999,data_width)), --add
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x"00001221", --nand
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x"00000FF0", --and
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x"0000F00F", --or
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x"00008754", --nor
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x"0000ADBF", --xor
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x"0000FECD", --not a
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x"0000CCDC", --not b
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std_logic_vector(to_signed(0,data_width)),--incr B
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std_logic_vector(to_signed(-1,data_width)),--incr A
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std_logic_vector(to_signed(0,data_width)),--sub A
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std_logic_vector(to_signed(0,data_width)),--sub B
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x"0000F0F0",--sll A
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x"0000ABAB",--sll B
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x"00004321"--noop
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);
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begin
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--define the operation of the module!
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A <= A_list(to_integer(op_cnt));
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b <= B_list(to_integer(op_cnt));
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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op_cnt <= (others => '0'); --zero counter on rst
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else
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op_cnt <= op_cnt + 1;
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end if;
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end if;
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end process;
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end behavioral;
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