65 lines
1.6 KiB
Verilog
65 lines
1.6 KiB
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 29.03.2020
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// Project name - PS04
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// Module name - DDS (direct digital synthesis)
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//
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// Detailed module description:
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// Aim of this problem set – to practice Direct Digital Synthesis in FPGA
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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// define connections to outside
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module dds_vhdl#( parameter
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phase_width = 4,
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data_width = 8
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)(
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input clk, //100mhz clock
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input rst, //rst
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input [1:0] control,
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input [phase_width - 1:0] phase_incr, //"frequency"
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output [phase_width - 1:0] phase_out,
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output [data_width - 1:0] signal_out);
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reg [phase_width - 1:0] r_phase_incr = 'd0;
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reg [phase_width - 1:0] r_phase_out = 'd0;
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// Phase increment – determines output frequency
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always@(posedge clk)begin
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if (rst) begin
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r_phase_incr <= 0; end
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else begin
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r_phase_incr <= phase_incr; end
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end
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// Phase accumulator – the «counter»
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always@(posedge clk)begin
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if (rst) begin
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r_phase_out <= 0; end
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else begin
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r_phase_out <= phase_out + phase_incr; end
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end
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// Look-up table – memory where waveform is stored
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lookuptable lookuptable (
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.phase( // mux
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(control== 0) ? 4'b0 :
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(control== 1) ? {2'b0, phase_out[phase_width - 3:0] } :
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(control== 2) ? {1'b0, phase_out[phase_width - 2:0] } :
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phase_out
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// end of MUX
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),
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.sin(signal_out),
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.cos());
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assign phase_out = r_phase_out;
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endmodule |