9 Commits

Include renames

Author	SHA1	Message	Date
Imants Pulkstenis	c8581dbe68	ps4 added	2020-03-29 21:08:14 +03:00
Imants Pulkstenis	8ee46486e8	add *.vcd file for GTKWave	2020-02-27 20:50:56 +02:00
Imants Pulkstenis	a29e888084	FSM picture	2020-02-24 00:53:46 +02:00
Imants Pulkstenis	5d5a40afe4	minor changes	2020-02-24 00:18:10 +02:00
Imants Pulkstenis	71b037e9fe	file raname	2020-02-24 00:14:20 +02:00
Imants Pulkstenis	22851efc71	VHDL Problem set 3	2020-02-23 23:58:12 +02:00
Imants Pulkstenis	fcc5a0b050	Compleated Verilog file and started working un VHDL	2020-02-23 22:40:30 +02:00
Imants Pulkstenis	c42e0654da	add aditional else if for MR_GREEN_1 state	2020-02-23 19:18:36 +02:00
Imants Pulkstenis	e6cbc865aa	Add Problem set 3	2020-02-23 19:12:32 +02:00