58 lines
2.9 KiB
Plaintext
58 lines
2.9 KiB
Plaintext
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
|
|
# Your use of Altera Corporation's design tools, logic functions
|
|
# and other software and tools, and its AMPP partner logic
|
|
# functions, and any output files from any of the foregoing
|
|
# (including device programming or simulation files), and any
|
|
# associated documentation or information are expressly subject
|
|
# to the terms and conditions of the Altera Program License
|
|
# Subscription Agreement, the Altera Quartus II License Agreement,
|
|
# the Altera MegaCore Function License Agreement, or other
|
|
# applicable license agreement, including, without limitation,
|
|
# that your use is for the sole purpose of programming logic
|
|
# devices manufactured by Altera and sold by Altera or its
|
|
# authorized distributors. Please refer to the applicable
|
|
# agreement for further details.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Quartus II 64-Bit
|
|
# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
|
|
# Date created = 11:44:46 February 25, 2017
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Notes:
|
|
#
|
|
# 1) The default values for assignments are stored in the file:
|
|
# ps02_assignment_defaults.qdf
|
|
# If this file doesn't exist, see file:
|
|
# assignment_defaults.qdf
|
|
#
|
|
# 2) Altera recommends that you do not modify this file. This
|
|
# file is updated automatically by the Quartus II software
|
|
# and any changes you make may be lost or overwritten.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
|
|
|
|
set_global_assignment -name FAMILY "Cyclone V"
|
|
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
|
|
set_global_assignment -name TOP_LEVEL_ENTITY ps02
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:46 FEBRUARY 25, 2017"
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
|
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
|
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
|
set_global_assignment -name VHDL_FILE alu.vhd
|
|
set_global_assignment -name VHDL_FILE ps02.vhd
|
|
set_global_assignment -name VHDL_FILE ps02_siggen.vhd
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |