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Add files for FIR and IIR filter - not tested

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This commit is contained in:
Imants Pulkstenis
2020-06-09 22:28:53 +03:00
parent 01e4a4b6d3
commit 682207dfa1
66 changed files with 13930 additions and 43 deletions
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ld3/dds_vhdl/fir.spd
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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file path="fir_sim/dspba_library_package.vhd" type="VHDL" />
<file path="fir_sim/dspba_library.vhd" type="VHDL" />
<file path="fir_sim/auk_dspip_math_pkg_hpfir.vhd" type="VHDL" />
<file path="fir_sim/auk_dspip_lib_pkg_hpfir.vhd" type="VHDL" />
<file
path="fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd"
type="VHDL" />
<file path="fir_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd" type="VHDL" />
<file
path="fir_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"
type="VHDL" />
<file path="fir_sim/auk_dspip_roundsat_hpfir.vhd" type="VHDL" />
<file path="fir_sim/altera_avalon_sc_fifo.v" type="VERILOG" />
<file path="fir_sim/fir_rtl_core.vhd" type="VHDL" />
<file path="fir_sim/fir_ast.vhd" type="VHDL" />
<file path="fir_sim/fir.vhd" type="VHDL" />
<file path="fir_sim/fir_nativelink.tcl" type="OTHER" />
<file path="fir_sim/fir_msim.tcl" type="OTHER" />
<file path="fir_sim/fir_tb.vhd" type="VHDL" />
<file path="fir_sim/fir_mlab.m" type="OTHER" />
<file path="fir_sim/fir_model.m" type="OTHER" />
<file path="fir_sim/fir_coef_int.txt" type="OTHER" />
<file path="fir_sim/fir_input.txt" type="OTHER" />
<file path="fir_sim/fir_param.txt" type="OTHER" />
<topLevel name="fir" />
<deviceFamily name="cyclonev" />
</simPackage>