30 lines
1.3 KiB
XML
30 lines
1.3 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file path="fir_sim/dspba_library_package.vhd" type="VHDL" />
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<file path="fir_sim/dspba_library.vhd" type="VHDL" />
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<file path="fir_sim/auk_dspip_math_pkg_hpfir.vhd" type="VHDL" />
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<file path="fir_sim/auk_dspip_lib_pkg_hpfir.vhd" type="VHDL" />
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<file
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path="fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd"
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type="VHDL" />
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<file path="fir_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd" type="VHDL" />
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<file
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path="fir_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"
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type="VHDL" />
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<file path="fir_sim/auk_dspip_roundsat_hpfir.vhd" type="VHDL" />
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<file path="fir_sim/altera_avalon_sc_fifo.v" type="VERILOG" />
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<file path="fir_sim/fir_rtl_core.vhd" type="VHDL" />
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<file path="fir_sim/fir_ast.vhd" type="VHDL" />
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<file path="fir_sim/fir.vhd" type="VHDL" />
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<file path="fir_sim/fir_nativelink.tcl" type="OTHER" />
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<file path="fir_sim/fir_msim.tcl" type="OTHER" />
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<file path="fir_sim/fir_tb.vhd" type="VHDL" />
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<file path="fir_sim/fir_mlab.m" type="OTHER" />
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<file path="fir_sim/fir_model.m" type="OTHER" />
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<file path="fir_sim/fir_coef_int.txt" type="OTHER" />
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<file path="fir_sim/fir_input.txt" type="OTHER" />
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<file path="fir_sim/fir_param.txt" type="OTHER" />
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<topLevel name="fir" />
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<deviceFamily name="cyclonev" />
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</simPackage>
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