diff --git a/ld3/dds_vhdl/IIF.vhd b/ld3/dds_vhdl/IIF.vhd new file mode 100644 index 0000000..1797f1e --- /dev/null +++ b/ld3/dds_vhdl/IIF.vhd @@ -0,0 +1,226 @@ +-- ------------------------------------------------------------- +-- +-- File Name: iif_hdl\ld3_fixed_point2\IIF.vhd +-- Created: 2020-06-09 20:33:43 +-- +-- Generated by MATLAB 9.3 and HDL Coder 3.11 +-- +-- +-- ------------------------------------------------------------- +-- Rate and Clocking Details +-- ------------------------------------------------------------- +-- Model base rate: 4.53515e-05 +-- Target subsystem base rate: 4.53515e-05 +-- +-- +-- Clock Enable Sample Time +-- ------------------------------------------------------------- +-- ce_out 4.53515e-05 +-- ------------------------------------------------------------- +-- +-- +-- Output Signal Clock Enable Sample Time +-- ------------------------------------------------------------- +-- Out1 ce_out 4.53515e-05 +-- ------------------------------------------------------------- +-- +-- ------------------------------------------------------------- + + +-- ------------------------------------------------------------- +-- +-- Module: IIF +-- Source Path: ld3_fixed_point2/IIF +-- Hierarchy Level: 0 +-- +-- ------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY IIF IS + PORT( clk : IN std_logic; + reset : IN std_logic; + clk_enable : IN std_logic; + In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 + ce_out : OUT std_logic; + Out1 : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14 + ); +END IIF; + + +ARCHITECTURE rtl OF IIF IS + + -- Signals + SIGNAL enb : std_logic; + SIGNAL kconst : signed(15 DOWNTO 0); -- sfix16_En20 + SIGNAL kconst_1 : signed(15 DOWNTO 0); -- sfix16_En20 + SIGNAL In1_signed : signed(15 DOWNTO 0); -- sfix16_En14 + SIGNAL Subtract1_out1 : signed(15 DOWNTO 0); -- sfix16_En9 + SIGNAL Delay1_out1 : signed(15 DOWNTO 0); -- sfix16_En9 + SIGNAL a_3_mul_temp : signed(31 DOWNTO 0); -- sfix32_En24 + SIGNAL a_3_out1 : signed(15 DOWNTO 0); -- sfix16_En10 + SIGNAL a_2_mul_temp : signed(31 DOWNTO 0); -- sfix32_En23 + SIGNAL a_2_out1 : signed(15 DOWNTO 0); -- sfix16_En9 + SIGNAL Subtract2_sub_cast : signed(31 DOWNTO 0); -- sfix32_En14 + SIGNAL Subtract2_sub_cast_1 : signed(31 DOWNTO 0); -- sfix32_En14 + SIGNAL Subtract2_sub_temp : signed(31 DOWNTO 0); -- sfix32_En14 + SIGNAL Subtract2_out1 : signed(15 DOWNTO 0); -- sfix16_En9 + SIGNAL Subtract1_sub_cast : signed(31 DOWNTO 0); -- sfix32_En10 + SIGNAL Subtract1_sub_cast_1 : signed(31 DOWNTO 0); -- sfix32_En10 + SIGNAL Subtract1_sub_temp : signed(31 DOWNTO 0); -- sfix32_En10 + SIGNAL Subtract1_out1_1 : signed(15 DOWNTO 0); -- sfix16_En9 + SIGNAL b_1_mul_temp : signed(31 DOWNTO 0); -- sfix32_En29 + SIGNAL b_1_out1 : signed(15 DOWNTO 0); -- sfix16_En15 + SIGNAL b_1_out1_1 : signed(15 DOWNTO 0); -- sfix16_En15 + SIGNAL b_2_out1 : signed(15 DOWNTO 0); -- sfix16_En14 + SIGNAL Sum_add_cast : signed(31 DOWNTO 0); -- sfix32_En15 + SIGNAL Sum_add_cast_1 : signed(31 DOWNTO 0); -- sfix32_En15 + SIGNAL Sum_add_temp : signed(31 DOWNTO 0); -- sfix32_En15 + SIGNAL Sum_out1 : signed(15 DOWNTO 0); -- sfix16_En15 + SIGNAL kconst_2 : signed(15 DOWNTO 0); -- sfix16_En20 + SIGNAL kconst_3 : signed(15 DOWNTO 0); -- sfix16_En20 + SIGNAL Delay1_out1_1 : signed(15 DOWNTO 0); -- sfix16_En9 + SIGNAL b_3_mul_temp : signed(31 DOWNTO 0); -- sfix32_En29 + SIGNAL b_3_out1 : signed(15 DOWNTO 0); -- sfix16_En15 + SIGNAL b_3_out1_1 : signed(15 DOWNTO 0); -- sfix16_En15 + SIGNAL Sum1_add_cast : signed(31 DOWNTO 0); -- sfix32_En15 + SIGNAL Sum1_add_cast_1 : signed(31 DOWNTO 0); -- sfix32_En15 + SIGNAL Sum1_add_temp : signed(31 DOWNTO 0); -- sfix32_En15 + SIGNAL Sum1_out1 : signed(15 DOWNTO 0); -- sfix16_En14 + + ATTRIBUTE multstyle : string; + +BEGIN + kconst <= to_signed(16#6CF4#, 16); + + enb <= clk_enable; + + HwModeRegister_process : PROCESS (clk, reset) + BEGIN + IF reset = '1' THEN + kconst_1 <= to_signed(16#0000#, 16); + ELSIF clk'EVENT AND clk = '1' THEN + IF enb = '1' THEN + kconst_1 <= kconst; + END IF; + END IF; + END PROCESS HwModeRegister_process; + + + In1_signed <= signed(In1); + + Delay1_process : PROCESS (clk, reset) + BEGIN + IF reset = '1' THEN + Delay1_out1 <= to_signed(16#0000#, 16); + ELSIF clk'EVENT AND clk = '1' THEN + IF enb = '1' THEN + Delay1_out1 <= Subtract1_out1; + END IF; + END IF; + END PROCESS Delay1_process; + + + a_3_mul_temp <= to_signed(16#7934#, 16) * Delay1_out1; + a_3_out1 <= a_3_mul_temp(29 DOWNTO 14); + + a_2_mul_temp <= to_signed(-16#5E65#, 16) * Subtract1_out1; + a_2_out1 <= a_2_mul_temp(29 DOWNTO 14); + + Subtract2_sub_cast <= resize(In1_signed, 32); + Subtract2_sub_cast_1 <= resize(a_2_out1 & '0' & '0' & '0' & '0' & '0', 32); + Subtract2_sub_temp <= Subtract2_sub_cast - Subtract2_sub_cast_1; + Subtract2_out1 <= Subtract2_sub_temp(20 DOWNTO 5); + + Subtract1_sub_cast <= resize(Subtract2_out1 & '0', 32); + Subtract1_sub_cast_1 <= resize(a_3_out1, 32); + Subtract1_sub_temp <= Subtract1_sub_cast - Subtract1_sub_cast_1; + Subtract1_out1_1 <= Subtract1_sub_temp(16 DOWNTO 1); + + reduced_process : PROCESS (clk, reset) + BEGIN + IF reset = '1' THEN + Subtract1_out1 <= to_signed(16#0000#, 16); + ELSIF clk'EVENT AND clk = '1' THEN + IF enb = '1' THEN + Subtract1_out1 <= Subtract1_out1_1; + END IF; + END IF; + END PROCESS reduced_process; + + + b_1_mul_temp <= kconst_1 * Subtract1_out1; + b_1_out1 <= b_1_mul_temp(29 DOWNTO 14); + + PipelineRegister_process : PROCESS (clk, reset) + BEGIN + IF reset = '1' THEN + b_1_out1_1 <= to_signed(16#0000#, 16); + ELSIF clk'EVENT AND clk = '1' THEN + IF enb = '1' THEN + b_1_out1_1 <= b_1_out1; + END IF; + END IF; + END PROCESS PipelineRegister_process; + + + b_2_out1 <= to_signed(16#0000#, 16); + + Sum_add_cast <= resize(b_1_out1_1, 32); + Sum_add_cast_1 <= resize(b_2_out1 & '0', 32); + Sum_add_temp <= Sum_add_cast + Sum_add_cast_1; + Sum_out1 <= Sum_add_temp(15 DOWNTO 0); + + kconst_2 <= to_signed(-16#6CF4#, 16); + + HwModeRegister2_process : PROCESS (clk, reset) + BEGIN + IF reset = '1' THEN + kconst_3 <= to_signed(16#0000#, 16); + ELSIF clk'EVENT AND clk = '1' THEN + IF enb = '1' THEN + kconst_3 <= kconst_2; + END IF; + END IF; + END PROCESS HwModeRegister2_process; + + + HwModeRegister3_process : PROCESS (clk, reset) + BEGIN + IF reset = '1' THEN + Delay1_out1_1 <= to_signed(16#0000#, 16); + ELSIF clk'EVENT AND clk = '1' THEN + IF enb = '1' THEN + Delay1_out1_1 <= Delay1_out1; + END IF; + END IF; + END PROCESS HwModeRegister3_process; + + + b_3_mul_temp <= kconst_3 * Delay1_out1_1; + b_3_out1 <= b_3_mul_temp(29 DOWNTO 14); + + PipelineRegister1_process : PROCESS (clk, reset) + BEGIN + IF reset = '1' THEN + b_3_out1_1 <= to_signed(16#0000#, 16); + ELSIF clk'EVENT AND clk = '1' THEN + IF enb = '1' THEN + b_3_out1_1 <= b_3_out1; + END IF; + END IF; + END PROCESS PipelineRegister1_process; + + + Sum1_add_cast <= resize(Sum_out1, 32); + Sum1_add_cast_1 <= resize(b_3_out1_1, 32); + Sum1_add_temp <= Sum1_add_cast + Sum1_add_cast_1; + Sum1_out1 <= Sum1_add_temp(16 DOWNTO 1); + + Out1 <= std_logic_vector(Sum1_out1); + + ce_out <= clk_enable; + +END rtl; + diff --git a/ld3/dds_vhdl/fir.bsf b/ld3/dds_vhdl/fir.bsf new file mode 100644 index 0000000..52e1602 --- /dev/null +++ b/ld3/dds_vhdl/fir.bsf @@ -0,0 +1,114 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 384 216) + (text "fir" (rect 186 -1 194 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 200 20 212)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8))) + (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 144 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8))) + (text "reset_n" (rect 4 101 46 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 144 112)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "ast_sink_data[15..0]" (rect 0 0 79 12)(font "Arial" (font_size 8))) + (text "ast_sink_data[15..0]" (rect 4 141 124 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 144 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "ast_sink_valid" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "ast_sink_valid" (rect 4 157 88 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 144 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "ast_sink_error[1..0]" (rect 0 0 77 12)(font "Arial" (font_size 8))) + (text "ast_sink_error[1..0]" (rect 4 173 124 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 144 184)(line_width 3)) + ) + (port + (pt 384 72) + (output) + (text "ast_source_data[36..0]" (rect 0 0 92 12)(font "Arial" (font_size 8))) + (text "ast_source_data[36..0]" (rect 268 61 400 72)(font "Arial" (font_size 8))) + (line (pt 384 72)(pt 224 72)(line_width 3)) + ) + (port + (pt 384 88) + (output) + (text "ast_source_valid" (rect 0 0 68 12)(font "Arial" (font_size 8))) + (text "ast_source_valid" (rect 297 77 393 88)(font "Arial" (font_size 8))) + (line (pt 384 88)(pt 224 88)(line_width 1)) + ) + (port + (pt 384 104) + (output) + (text "ast_source_error[1..0]" (rect 0 0 89 12)(font "Arial" (font_size 8))) + (text "ast_source_error[1..0]" (rect 273 93 405 104)(font "Arial" (font_size 8))) + (line (pt 384 104)(pt 224 104)(line_width 3)) + ) + (drawing + (text "clk" (rect 129 43 276 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 149 67 316 144)(font "Arial" (color 0 0 0))) + (text "rst" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 149 107 340 224)(font "Arial" (color 0 0 0))) + (text "avalon_streaming_sink" (rect 10 123 146 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "data" (rect 149 147 322 304)(font "Arial" (color 0 0 0))) + (text "valid" (rect 149 163 328 336)(font "Arial" (color 0 0 0))) + (text "error" (rect 149 179 328 368)(font "Arial" (color 0 0 0))) + (text "avalon_streaming_source" (rect 225 43 588 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "data" (rect 203 67 430 144)(font "Arial" (color 0 0 0))) + (text "valid" (rect 201 83 432 176)(font "Arial" (color 0 0 0))) + (text "error" (rect 199 99 428 208)(font "Arial" (color 0 0 0))) + (text " altera_fir_compiler_ii " (rect 289 200 722 410)(font "Arial" )) + (line (pt 144 32)(pt 224 32)(line_width 1)) + (line (pt 224 32)(pt 224 200)(line_width 1)) + (line (pt 144 200)(pt 224 200)(line_width 1)) + (line (pt 144 32)(pt 144 200)(line_width 1)) + (line (pt 145 52)(pt 145 76)(line_width 1)) + (line (pt 146 52)(pt 146 76)(line_width 1)) + (line (pt 145 92)(pt 145 116)(line_width 1)) + (line (pt 146 92)(pt 146 116)(line_width 1)) + (line (pt 145 132)(pt 145 188)(line_width 1)) + (line (pt 146 132)(pt 146 188)(line_width 1)) + (line (pt 223 52)(pt 223 108)(line_width 1)) + (line (pt 222 52)(pt 222 108)(line_width 1)) + (line (pt 0 0)(pt 384 0)(line_width 1)) + (line (pt 384 0)(pt 384 216)(line_width 1)) + (line (pt 0 216)(pt 384 216)(line_width 1)) + (line (pt 0 0)(pt 0 216)(line_width 1)) + ) +) diff --git a/ld3/dds_vhdl/fir.cmp b/ld3/dds_vhdl/fir.cmp new file mode 100644 index 0000000..7dbddab --- /dev/null +++ b/ld3/dds_vhdl/fir.cmp @@ -0,0 +1,13 @@ + component fir is + port ( + clk : in std_logic := 'X'; -- clk + reset_n : in std_logic := 'X'; -- reset_n + ast_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data + ast_sink_valid : in std_logic := 'X'; -- valid + ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error + ast_source_data : out std_logic_vector(36 downto 0); -- data + ast_source_valid : out std_logic; -- valid + ast_source_error : out std_logic_vector(1 downto 0) -- error + ); + end component fir; + diff --git a/ld3/dds_vhdl/fir.qip b/ld3/dds_vhdl/fir.qip new file mode 100644 index 0000000..89e45e4 --- /dev/null +++ b/ld3/dds_vhdl/fir.qip @@ -0,0 +1,102 @@ +set_global_assignment -entity "fir" -library "fir" -name IP_TOOL_NAME "altera_fir_compiler_ii" +set_global_assignment -entity "fir" -library "fir" -name IP_TOOL_VERSION "19.1" +set_global_assignment -entity "fir" -library "fir" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "fir" -name MISC_FILE [file join $::quartus(qip_path) "fir.cmp"] +set_global_assignment -entity "fir" -library "fir" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "fir" -library "fir" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "fir" -library "fir" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "fir" -library "fir" -name IP_COMPONENT_NAME "Zmly" +set_global_assignment -entity "fir" -library "fir" -name IP_COMPONENT_DISPLAY_NAME "RklSIElJ" +set_global_assignment -entity "fir" -library "fir" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "fir" -library "fir" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "fir" -library "fir" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "fir" -library "fir" -name IP_COMPONENT_VERSION "MTkuMQ==" +set_global_assignment -entity "fir" -library "fir" -name IP_COMPONENT_DESCRIPTION "RklSIElJIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_NAME "ZmlyXzAwMDI=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_DISPLAY_NAME "RklSIElJ" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_VERSION "MTkuMQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_DESCRIPTION "RklSIElJIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZmlsdGVyVHlwZQ==::c2luZ2xl::RmlsdGVyIFR5cGU=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW50ZXJwRmFjdG9y::MQ==::SW50ZXJwb2xhdGlvbiBGYWN0b3I=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZGVjaW1GYWN0b3I=::MQ==::RGVjaW1hdGlvbiBGYWN0b3I=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "c3ltbWV0cnlNb2Rl::bnN5bQ==::U3ltbWV0cnk=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "TF9iYW5kc0ZpbHRlcg==::MQ==::TC10aCBCYW5kIEZpbHRlcg==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRDaGFubmVsTnVt::MQ==::TWF4IE51bWJlciBvZiBDaGFubmVscw==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::MTAw::Q2xvY2sgUmF0ZQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2xvY2tTbGFjaw==::MA==::Q2xvY2sgU2xhY2s=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRSYXRl::MTAw::SW5wdXQgU2FtcGxlIFJhdGUgKE1TUFMp" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZSZWxvYWQ=::ZmFsc2U=::Q29lZmZpY2llbnRzIFJlbG9hZA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZpY2llbnRSZWFkYmFjaw==::ZmFsc2U=::Y29lZmZpY2llbnRSZWFkYmFjaw==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZpY2llbnRXcml0ZWFibGU=::ZmFsc2U=::Y29lZmZpY2llbnRXcml0ZWFibGU=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "YnVzRGF0YVdpZHRo::MTY=::YnVzRGF0YVdpZHRo" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "YmFja1ByZXNzdXJl::ZmFsc2U=::QmFjayBQcmVzc3VyZSBTdXBwb3J0" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5::Q3ljbG9uZSBW::RGV2aWNlIEZhbWlseQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "c3BlZWRHcmFkZQ==::bWVkaXVt::U3BlZWQgR3JhZGU=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZGVsYXlSQU1CbG9ja1RocmVzaG9sZA==::MjA=::TWVtb3J5IEJsb2NrIFRocmVzaG9sZA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZHVhbE1lbURpc3RSQU1UaHJlc2hvbGQ=::MTI4MA==::RHVhbCBQb3J0IFJBTSBUaHJlc2hvbGQ=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "bVJBTVRocmVzaG9sZA==::MTAwMDAwMA==::TGFyZ2UgUkFNIFRocmVzaG9sZA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aGFyZE11bHRpcGxpZXJUaHJlc2hvbGQ=::LTE=::SGFyZCBNdWx0aXBsaWVyIFRocmVzaG9sZA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "cmVjb25maWd1cmFibGU=::ZmFsc2U=::UmVjb25maWd1cmFibGUgQ2FycmllciBNb2Rl" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "bnVtX21vZGVz::Mg==::TnVtYmVyIG9mIE1vZGVz" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "TW9kZVdpZHRo::MA==::TW9kZVdpZHRo" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "cmVjb25maWd1cmFibGVfbGlzdA==::MA==::Q2hvb3NlIE1vZGUgdG8gRWRpdA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "TU9ERV9TVFJJTkc=::Tm9uZSBTZXQ=::TU9ERV9TVFJJTkdfRElTUExBWQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "bW9kZUZvcm1hdHRlZA==::LS0=::bW9kZUZvcm1hdHRlZA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2hhbm5lbE1vZGVz::MCwxLDIsMw==::Q2hhbm5lbCBNb2RlIE9yZGVy" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRUeXBl::ZnJhYw==::SW5wdXQgVHlwZQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRCaXRXaWR0aA==::MTY=::SW5wdXQgV2lkdGg=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRGcmFjQml0V2lkdGg=::MTQ=::SW5wdXQgRnJhY3Rpb25hbCBXaWR0aA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWU=::LTAuMDA3MywtMC4wMDcxLC0wLjAwNTksLTAuMDAyNCwwLjAwNCwwLjAxMzIsMC4wMjMxLDAuMDMwMSwwLjAzMDIsMC4wMjA3LDAuMDAxNSwtMC4wMjQyLC0wLjA0OTgsLTAuMDY3NywtMC4wNzEyLC0wLjA1NzEsLTAuMDI2OSwwLjAxMjksMC4wNTI1LDAuMDgxNCwwLjA5MiwwLjA4MTQsMC4wNTI1LDAuMDEyOSwtMC4wMjY5LC0wLjA1NzEsLTAuMDcxMiwtMC4wNjc3LC0wLjA0OTgsLTAuMDI0MiwwLjAwMTUsMC4wMjA3LDAuMDMwMiwwLjAzMDEsMC4wMjMxLDAuMDEzMiwwLjAwNCwtMC4wMDI0LC0wLjAwNTksLTAuMDA3MSwtMC4wMDcz::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXM=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZOdW0=::NDE=::TnVtYmVyIG9mIENvZWZmaWNpZW50cw==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRSZWFsVmFsdWVJbWFn::MC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgLTAuMDUzMDA5MywgLTAuMDQ0OTgsIDAuMCwgMC4wNzQ5NjkzLCAwLjE1OTAzNCwgMC4yMjQ5MDcsIDAuMjQ5ODA5LCAwLjIyNDkwNywgMC4xNTkwMzQsIDAuMDc0OTY5MywgMC4wLCAtMC4wNDQ5OCwgLTAuMDUzMDA5MywgLTAuMDMyMTI4MywgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjAsIDAuMCwgMC4wLCAwLjA=::UmVhbCBDb2VmZmljaWVudCBWYWx1ZXMgKEltYWdpbmFyeSBDb21wb25lbnQp" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRTY2FsZVZhbHVl::LTAuMDA3Mjk0NjM0NjgyMjkyNjIxLC0wLjAwNzA5ODA4OTQ4MzAwMDY3MiwtMC4wMDU4OTYzNTU5Nzg3NTg0NjksLTAuMDAyMzk3ODUxNDMxMzYxNzc4LDAuMDAzOTk4MjkwOTExMzEwNTA1LDAuMDEzMTk2NjA2MjM4MTczNzE4LDAuMDIzMDk2ODY4NzA1MzY1MzE4LDAuMDMwMDk5NDkzMzc3MjgxMzMsMC4wMzAxOTQ5NTgxODgzNjU5OSwwLjAyMDY5OTAxNzI3NDAwMzU0MiwwLjAwMTQ5OTM1OTA5MTc0MTQzOTMsLTAuMDI0MTk3NTIxODIxNDAwMjMyLC0wLjA0OTc5ODkzNzkyMzQ1NzI0LC0wLjA2NzY5NTc4MjIxMzI2OTg2LC0wLjA3MTE5OTkwMjMzNzc4OTE4LC0wLjA1NzA5OTE4ODE4Mjg3MjQ5LC0wLjAyNjg5ODYxNDQxNzM4Mzg3NSwwLjAxMjg5ODk4MDY1MDY3NDQ4LDAuMDUyNDk0NDE0OTQyMzE4MjYsMC4wODEzOTc3OTAzOTI0ODAwMiwwLjA5MTk5NDM4NDQyMjg3NzM4LDAuMDgxMzk3NzkwMzkyNDgwMDIsMC4wNTI0OTQ0MTQ5NDIzMTgyNiwwLjAxMjg5ODk4MDY1MDY3NDQ4LC0wLjAyNjg5ODYxNDQxNzM4Mzg3NSwtMC4wNTcwOTkxODgxODI4NzI0OSwtMC4wNzExOTk5MDIzMzc3ODkxOCwtMC4wNjc2OTU3ODIyMTMyNjk4NiwtMC4wNDk3OTg5Mzc5MjM0NTcyNCwtMC4wMjQxOTc1MjE4MjE0MDAyMzIsMC4wMDE0OTkzNTkwOTE3NDE0MzkzLDAuMDIwNjk5MDE3Mjc0MDAzNTQyLDAuMDMwMTk0OTU4MTg4MzY1OTksMC4wMzAwOTk0OTMzNzcyODEzMywwLjAyMzA5Njg2ODcwNTM2NTMxOCwwLjAxMzE5NjYwNjIzODE3MzcxOCwwLjAwMzk5ODI5MDkxMTMxMDUwNSwtMC4wMDIzOTc4NTE0MzEzNjE3NzgsLTAuMDA1ODk2MzU1OTc4NzU4NDY5LC0wLjAwNzA5ODA4OTQ4MzAwMDY3MiwtMC4wMDcyOTQ2MzQ2ODIyOTI2MjE=::U2NhbGVkIENvZWZmaWNpZW50IFZhbHVlcw==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRTY2FsZVZhbHVlSW1hZw==::MC4wLDAuMCwwLjAsMC4wLDAuMCwwLjAsMC4wLDAuMA==::U2NhbGVkIENvZWZmaWNpZW50IFZhbHVlcyAoSW1hZ2luYXJ5IENvbXBvbmVudCk=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRGaXhlZFZhbHVl::LTEyOTksLTEyNjQsLTEwNTAsLTQyNyw3MTIsMjM1MCw0MTEzLDUzNjAsNTM3NywzNjg2LDI2NywtNDMwOSwtODg2OCwtMTIwNTUsLTEyNjc5LC0xMDE2OCwtNDc5MCwyMjk3LDkzNDgsMTQ0OTUsMTYzODIsMTQ0OTUsOTM0OCwyMjk3LC00NzkwLC0xMDE2OCwtMTI2NzksLTEyMDU1LC04ODY4LC00MzA5LDI2NywzNjg2LDUzNzcsNTM2MCw0MTEzLDIzNTAsNzEyLC00MjcsLTEwNTAsLTEyNjQsLTEyOTk=::Rml4ZWQtcG9pbnQgQ29lZmZpY2llbnQgVmFsdWVz" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZTZXRGaXhlZFZhbHVlSW1hZw==::MCwwLDAsMCwwLDAsMCww::Rml4ZWQtcG9pbnQgQ29lZmZpY2llbnQgVmFsdWVzIChJbWFnaW5hcnkgQ29tcG9uZW50KQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZTY2FsaW5n::YXV0bw==::Q29lZmZpY2llbnQgU2NhbGluZw==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZUeXBl::ZnJhYw==::Q29lZmZpY2llbnQgRGF0YSBUeXBl" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZGcmFjQml0V2lkdGg=::MTQ=::Q29lZmZpY2llbnQgRnJhY3Rpb25hbCBXaWR0aA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y29lZmZDb21wbGV4::ZmFsc2U=::Q29tcGxleCBDb2VmZmljaWVudHM=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "a2FyYXRzdWJh::ZmFsc2U=::S2FyYXRzdWJhIEltcGxlbWVudGF0aW9u" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "b3V0VHlwZQ==::ZnJhYw==::T3V0cHV0IFR5cGU=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "b3V0TVNCUm91bmQ=::dHJ1bmM=::U3BlY2lmaWVzIHdoZXRoZXIgdG8gdHJ1bmNhdGUgb3Igc2F0dXJhdGUgdGhlIG1vc3Qgc2lnbmlmaWNhbnQgYml0IChNU0IpLg==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "b3V0TXNiQml0UmVt::MA==::TVNCIEJpdHMgdG8gUmVtb3Zl" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "b3V0TFNCUm91bmQ=::dHJ1bmM=::U3BlY2lmaWVzIHdoZXRoZXIgdG8gdHJ1bmNhdGUgb3Igcm91bmQgdGhlIGxlYXN0IHNpZ25pZmljYW50IGJpdCAoTFNCKS4=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "b3V0THNiQml0UmVt::MA==::TFNCIEJpdHMgdG8gUmVtb3Zl" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "aW5wdXRJbnRlcmZhY2VOdW0=::MQ==::TnVtYmVyIG9mIFBhcmFsbGVsIElucHV0IFN5bWJvbHM=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "b3V0cHV0SW50ZXJmYWNlTnVt::MQ==::TnVtYmVyIG9mIFBhcmFsbGVsIE91dHB1dCBTeW1ib2xz" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2hhblBlcklucHV0SW50ZXJmYWNl::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBJbnB1dCBJbnRlcmZhY2U=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "Y2hhblBlck91dHB1dEludGVyZmFjZQ==::MQ==::TnVtYmVyIG9mIENoYW5uZWxzIHBlciBPdXRwdXQgSW50ZXJmYWNl" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeQ==::MTM=::bGF0ZW5jeQ==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "b3V0cHV0Zmlmb2RlcHRo::OA==::b3V0cHV0Zmlmb2RlcHRo" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZnVuY1Jlc3VsdA==::LWludGVycD0xIC1kZWNpbT0xIC1pbmN5Y2xlcz0xIC1sZW49NDEgLWJhbmtjb3VudD0xIC1uc3ltIC1uYmFuZD0xIC1jaGFucz0xIC1mYW1pbHk9IkN5Y2xvbmUgViIgCnx7fXwxfDF8MXwxfDM3fDI4fDEzfDR8bm9Db2RlfExVVFM6IDgzIERTUHM6IDQyIFJBTSBCaXRzOiAwfA==::ZnVuY1Jlc3VsdA==" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "YnVzQWRkcmVzc1dpZHRo::Ng==::YnVzQWRkcmVzc1dpZHRo" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "YmFua0NvdW50::MQ==::TnVtYmVyIG9mIENvZWZmaWNpZW50IEJhbmtz" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "YmFua0luV2lkdGg=::MA==::YmFua0luV2lkdGg=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "YmFua0Rpc3BsYXk=::MA==::YmFua0Rpc3BsYXk=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "bHV0Q291bnQ=::ODM=::TnVtYmVyIG9mIExVVHM=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZHNwQ291bnQ=::NDI=::TnVtYmVyIG9mIERTUHM=" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "bWVtQml0Q291bnQ=::MA==::TnVtYmVyIG9mIE1lbW9yeSBCaXRz" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_COMPONENT_PARAMETER "ZXJyb3JMaXN0::MA==::ZXJyb3JMaXN0" + +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/dspba_library_package.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/dspba_library.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/auk_dspip_math_pkg_hpfir.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/auk_dspip_lib_pkg_hpfir.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/auk_dspip_avalon_streaming_controller_hpfir.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/auk_dspip_avalon_streaming_sink_hpfir.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/auk_dspip_avalon_streaming_source_hpfir.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/auk_dspip_roundsat_hpfir.vhd"] +set_global_assignment -library "fir" -name VERILOG_FILE [file join $::quartus(qip_path) "fir/altera_avalon_sc_fifo.v"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/fir_0002_rtl_core.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/fir_0002_ast.vhd"] +set_global_assignment -library "fir" -name VHDL_FILE [file join $::quartus(qip_path) "fir/fir_0002.vhd"] + +set_global_assignment -entity "fir_0002" -library "fir" -name IP_TOOL_NAME "altera_fir_compiler_ii" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_TOOL_VERSION "19.1" +set_global_assignment -entity "fir_0002" -library "fir" -name IP_TOOL_ENV "mwpim" diff --git a/ld3/dds_vhdl/fir.sip b/ld3/dds_vhdl/fir.sip new file mode 100644 index 0000000..722b263 --- /dev/null +++ b/ld3/dds_vhdl/fir.sip @@ -0,0 +1,25 @@ +set_global_assignment -entity "fir" -library "lib_fir" -name IP_TOOL_NAME "altera_fir_compiler_ii" +set_global_assignment -entity "fir" -library "lib_fir" -name IP_TOOL_VERSION "19.1" +set_global_assignment -entity "fir" -library "lib_fir" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "lib_fir" -name SPD_FILE [file join $::quartus(sip_path) "fir.spd"] + +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/dspba_library_package.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/dspba_library.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/auk_dspip_math_pkg_hpfir.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/auk_dspip_lib_pkg_hpfir.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/auk_dspip_avalon_streaming_source_hpfir.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/auk_dspip_roundsat_hpfir.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/altera_avalon_sc_fifo.v"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_rtl_core.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_ast.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_nativelink.tcl"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_msim.tcl"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_tb.vhd"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_mlab.m"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_model.m"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_coef_int.txt"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_input.txt"] +set_global_assignment -library "lib_fir" -name MISC_FILE [file join $::quartus(sip_path) "fir_sim/fir_param.txt"] diff --git a/ld3/dds_vhdl/fir.spd b/ld3/dds_vhdl/fir.spd new file mode 100644 index 0000000..cd3ff80 --- /dev/null +++ b/ld3/dds_vhdl/fir.spd @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ld3/dds_vhdl/fir.vhd b/ld3/dds_vhdl/fir.vhd new file mode 100644 index 0000000..96df429 --- /dev/null +++ b/ld3/dds_vhdl/fir.vhd @@ -0,0 +1,123 @@ +-- megafunction wizard: %FIR II v19.1% +-- GENERATION: XML +-- fir.vhd + +-- Generated using ACDS version 19.1 670 + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity fir is + port ( + clk : in std_logic := '0'; -- clk.clk + reset_n : in std_logic := '0'; -- rst.reset_n + ast_sink_data : in std_logic_vector(15 downto 0) := (others => '0'); -- avalon_streaming_sink.data + ast_sink_valid : in std_logic := '0'; -- .valid + ast_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error + ast_source_data : out std_logic_vector(36 downto 0); -- avalon_streaming_source.data + ast_source_valid : out std_logic; -- .valid + ast_source_error : out std_logic_vector(1 downto 0) -- .error + ); +end entity fir; + +architecture rtl of fir is + component fir_0002 is + port ( + clk : in std_logic := 'X'; -- clk + reset_n : in std_logic := 'X'; -- reset_n + ast_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data + ast_sink_valid : in std_logic := 'X'; -- valid + ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error + ast_source_data : out std_logic_vector(36 downto 0); -- data + ast_source_valid : out std_logic; -- valid + ast_source_error : out std_logic_vector(1 downto 0) -- error + ); + end component fir_0002; + +begin + + fir_inst : component fir_0002 + port map ( + clk => clk, -- clk.clk + reset_n => reset_n, -- rst.reset_n + ast_sink_data => ast_sink_data, -- avalon_streaming_sink.data + ast_sink_valid => ast_sink_valid, -- .valid + ast_sink_error => ast_sink_error, -- .error + ast_source_data => ast_source_data, -- avalon_streaming_source.data + ast_source_valid => ast_source_valid, -- .valid + ast_source_error => ast_source_error -- .error + ); + +end architecture rtl; -- of fir +-- Retrieval info: +-- +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- IPFS_FILES : NONE diff --git a/ld3/dds_vhdl/fir/altera_avalon_sc_fifo.v b/ld3/dds_vhdl/fir/altera_avalon_sc_fifo.v new file mode 100644 index 0000000..0d57cc2 --- /dev/null +++ b/ld3/dds_vhdl/fir/altera_avalon_sc_fifo.v @@ -0,0 +1,915 @@ +// ----------------------------------------------------------- +// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your +// use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any +// output files any of the foregoing (including device programming or +// simulation files), and any associated documentation or information are +// expressly subject to the terms and conditions of the Altera Program +// License Subscription Agreement or other applicable license agreement, +// including, without limitation, that your use is for the sole purpose +// of programming logic devices manufactured by Altera and sold by Altera +// or its authorized distributors. Please refer to the applicable +// agreement for further details. +// +// Description: Single clock Avalon-ST FIFO. +// ----------------------------------------------------------- + +`timescale 1 ns / 1 ns + + +//altera message_off 10036 +module altera_avalon_sc_fifo +#( + // -------------------------------------------------- + // Parameters + // -------------------------------------------------- + parameter SYMBOLS_PER_BEAT = 1, + parameter BITS_PER_SYMBOL = 8, + parameter FIFO_DEPTH = 16, + parameter CHANNEL_WIDTH = 0, + parameter ERROR_WIDTH = 0, + parameter USE_PACKETS = 0, + parameter USE_FILL_LEVEL = 0, + parameter USE_STORE_FORWARD = 0, + parameter USE_ALMOST_FULL_IF = 0, + parameter USE_ALMOST_EMPTY_IF = 0, + + // -------------------------------------------------- + // Empty latency is defined as the number of cycles + // required for a write to deassert the empty flag. + // For example, a latency of 1 means that the empty + // flag is deasserted on the cycle after a write. + // + // Another way to think of it is the latency for a + // write to propagate to the output. + // + // An empty latency of 0 implies lookahead, which is + // only implemented for the register-based FIFO. + // -------------------------------------------------- + parameter EMPTY_LATENCY = 3, + parameter USE_MEMORY_BLOCKS = 1, + + // -------------------------------------------------- + // Internal Parameters + // -------------------------------------------------- + parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) +) +( + // -------------------------------------------------- + // Ports + // -------------------------------------------------- + input clk, + input reset, + + input [DATA_WIDTH-1: 0] in_data, + input in_valid, + input in_startofpacket, + input in_endofpacket, + input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, + input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, + input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, + output in_ready, + + output [DATA_WIDTH-1 : 0] out_data, + output reg out_valid, + output out_startofpacket, + output out_endofpacket, + output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, + output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, + output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, + input out_ready, + + input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, + input csr_write, + input csr_read, + input [31 : 0] csr_writedata, + output reg [31 : 0] csr_readdata, + + output wire almost_full_data, + output wire almost_empty_data +); + + // -------------------------------------------------- + // Local Parameters + // -------------------------------------------------- + localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); + localparam DEPTH = FIFO_DEPTH; + localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; + localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? + 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; + + // -------------------------------------------------- + // Internal Signals + // -------------------------------------------------- + genvar i; + + reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; + reg [ADDR_WIDTH-1 : 0] wr_ptr; + reg [ADDR_WIDTH-1 : 0] rd_ptr; + reg [DEPTH-1 : 0] mem_used; + + wire [ADDR_WIDTH-1 : 0] next_wr_ptr; + wire [ADDR_WIDTH-1 : 0] next_rd_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; + + wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; + + wire read; + wire write; + + reg empty; + reg next_empty; + reg full; + reg next_full; + + wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; + wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; + wire [PAYLOAD_WIDTH-1 : 0] in_payload; + reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; + reg [PAYLOAD_WIDTH-1 : 0] out_payload; + + reg internal_out_valid; + wire internal_out_ready; + + reg [ADDR_WIDTH : 0] fifo_fill_level; + reg [ADDR_WIDTH : 0] fill_level; + + reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; + wire [ADDR_WIDTH-1 : 0] curr_sop_ptr; + reg [23:0] almost_full_threshold; + reg [23:0] almost_empty_threshold; + reg [23:0] cut_through_threshold; + reg [15:0] pkt_cnt; + reg drop_on_error_en; + reg error_in_pkt; + reg pkt_has_started; + reg sop_has_left_fifo; + reg fifo_too_small_r; + reg pkt_cnt_eq_zero; + reg pkt_cnt_eq_one; + + wire wait_for_threshold; + reg pkt_mode; + wire wait_for_pkt; + wire ok_to_forward; + wire in_pkt_eop_arrive; + wire out_pkt_leave; + wire in_pkt_start; + wire in_pkt_error; + wire drop_on_error; + wire fifo_too_small; + wire out_pkt_sop_leave; + wire [31:0] max_fifo_size; + reg fifo_fill_level_lt_cut_through_threshold; + + // -------------------------------------------------- + // Define Payload + // + // Icky part where we decide which signals form the + // payload to the FIFO with generate blocks. + // -------------------------------------------------- + generate + if (EMPTY_WIDTH > 0) begin : gen_blk1 + assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; + assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; + end + else begin : gen_blk1_else + assign out_empty = in_error; + assign in_packet_signals = {in_startofpacket, in_endofpacket}; + assign {out_startofpacket, out_endofpacket} = out_packet_signals; + end + endgenerate + + generate + if (USE_PACKETS) begin : gen_blk2 + if (ERROR_WIDTH > 0) begin : gen_blk3 + if (CHANNEL_WIDTH > 0) begin : gen_blk4 + assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; + assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; + end + else begin : gen_blk4_else + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data, in_error}; + assign {out_packet_signals, out_data, out_error} = out_payload; + end + end + else begin : gen_blk3_else + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin : gen_blk5 + assign in_payload = {in_packet_signals, in_data, in_channel}; + assign {out_packet_signals, out_data, out_channel} = out_payload; + end + else begin : gen_blk5_else + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data}; + assign {out_packet_signals, out_data} = out_payload; + end + end + end + else begin : gen_blk2_else + assign out_packet_signals = 0; + if (ERROR_WIDTH > 0) begin : gen_blk6 + if (CHANNEL_WIDTH > 0) begin : gen_blk7 + assign in_payload = {in_data, in_error, in_channel}; + assign {out_data, out_error, out_channel} = out_payload; + end + else begin : gen_blk7_else + assign out_channel = in_channel; + assign in_payload = {in_data, in_error}; + assign {out_data, out_error} = out_payload; + end + end + else begin : gen_blk6_else + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin : gen_blk8 + assign in_payload = {in_data, in_channel}; + assign {out_data, out_channel} = out_payload; + end + else begin : gen_blk8_else + assign out_channel = in_channel; + assign in_payload = in_data; + assign out_data = out_payload; + end + end + end + endgenerate + + // -------------------------------------------------- + // Memory-based FIFO storage + // + // To allow a ready latency of 0, the read index is + // obtained from the next read pointer and memory + // outputs are unregistered. + // + // If the empty latency is 1, we infer bypass logic + // around the memory so writes propagate to the + // outputs on the next cycle. + // + // Do not change the way this is coded: Quartus needs + // a perfect match to the template, and any attempt to + // refactor the two always blocks into one will break + // memory inference. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9 + + if (EMPTY_LATENCY == 1) begin : gen_blk10 + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] = in_payload; + + internal_out_payload = mem[mem_rd_ptr]; + end + + end else begin : gen_blk10_else + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] <= in_payload; + + internal_out_payload <= mem[mem_rd_ptr]; + end + + end + + assign mem_rd_ptr = next_rd_ptr; + + end else begin : gen_blk9_else + + // -------------------------------------------------- + // Register-based FIFO storage + // + // Uses a shift register as the storage element. Each + // shift register slot has a bit which indicates if + // the slot is occupied (credit to Sam H for the idea). + // The occupancy bits are contiguous and start from the + // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep + // FIFO. + // + // Each slot is enabled during a read or when it + // is unoccupied. New data is always written to every + // going-to-be-empty slot (we keep track of which ones + // are actually useful with the occupancy bits). On a + // read we shift occupied slots. + // + // The exception is the last slot, which always gets + // new data when it is unoccupied. + // -------------------------------------------------- + for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg + always @(posedge clk or posedge reset) begin + if (reset) begin + mem[i] <= 0; + end + else if (read || !mem_used[i]) begin + if (!mem_used[i+1]) + mem[i] <= in_payload; + else + mem[i] <= mem[i+1]; + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + mem[DEPTH-1] <= 0; + end + else begin + if (DEPTH == 1) begin + if (write) + mem[DEPTH-1] <= in_payload; + end + else if (!mem_used[DEPTH-1]) + mem[DEPTH-1] <= in_payload; + end + end + + end + endgenerate + + assign read = internal_out_ready && internal_out_valid && ok_to_forward; + assign write = in_ready && in_valid; + + // -------------------------------------------------- + // Pointer Management + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11 + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + + end else begin : gen_blk11_else + + // -------------------------------------------------- + // Shift Register Occupancy Bits + // + // Consider a 4-deep FIFO with 2 entries: 0011 + // On a read and write, do not modify the bits. + // On a write, left-shift the bits to get 0111. + // On a read, right-shift the bits to get 0001. + // + // Also, on a write we set bit0 (the head), while + // clearing the tail on a read. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[0] <= 0; + end + else begin + if (write ^ read) begin + if (write) + mem_used[0] <= 1; + else if (read) begin + if (DEPTH > 1) + mem_used[0] <= mem_used[1]; + else + mem_used[0] <= 0; + end + end + end + end + + if (DEPTH > 1) begin : gen_blk12 + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[DEPTH-1] <= 0; + end + else begin + if (write ^ read) begin + mem_used[DEPTH-1] <= 0; + if (write) + mem_used[DEPTH-1] <= mem_used[DEPTH-2]; + end + end + end + end + + for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic + always @(posedge clk, posedge reset) begin + if (reset) begin + mem_used[i] <= 0; + end + else begin + if (write ^ read) begin + if (write) + mem_used[i] <= mem_used[i-1]; + else if (read) + mem_used[i] <= mem_used[i+1]; + end + end + end + end + + end + endgenerate + + + // -------------------------------------------------- + // Memory FIFO Status Management + // + // Generates the full and empty signals from the + // pointers. The FIFO is full when the next write + // pointer will be equal to the read pointer after + // a write. Reading from a FIFO clears full. + // + // The FIFO is empty when the next read pointer will + // be equal to the write pointer after a read. Writing + // to a FIFO clears empty. + // + // A simultaneous read and write must not change any of + // the empty or full flags unless there is a drop on error event. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13 + + always @* begin + next_full = full; + next_empty = empty; + + if (read && !write) begin + next_full = 1'b0; + + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + + if (write && !read) begin + if (!drop_on_error) + next_empty = 1'b0; + else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo + next_empty = 1'b1; + + if (incremented_wr_ptr == rd_ptr && !drop_on_error) + next_full = 1'b1; + end + + if (write && read && drop_on_error) begin + if (curr_sop_ptr == next_rd_ptr) + next_empty = 1'b1; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + empty <= 1; + full <= 0; + end + else begin + empty <= next_empty; + full <= next_full; + end + end + + end else begin : gen_blk13_else + // -------------------------------------------------- + // Register FIFO Status Management + // + // Full when the tail occupancy bit is 1. Empty when + // the head occupancy bit is 0. + // -------------------------------------------------- + always @* begin + full = mem_used[DEPTH-1]; + empty = !mem_used[0]; + + // ------------------------------------------ + // For a single slot FIFO, reading clears the + // full status immediately. + // ------------------------------------------ + if (DEPTH == 1) + full = mem_used[0] && !read; + + internal_out_payload = mem[0]; + + // ------------------------------------------ + // Writes clear empty immediately for lookahead modes. + // Note that we use in_valid instead of write to avoid + // combinational loops (in lookahead mode, qualifying + // with in_ready is meaningless). + // + // In a 1-deep FIFO, a possible combinational loop runs + // from write -> out_valid -> out_ready -> write + // ------------------------------------------ + if (EMPTY_LATENCY == 0) begin + empty = !mem_used[0] && !in_valid; + + if (!mem_used[0] && in_valid) + internal_out_payload = in_payload; + end + end + + end + endgenerate + + // -------------------------------------------------- + // Avalon-ST Signals + // + // The in_ready signal is straightforward. + // + // To match memory latency when empty latency > 1, + // out_valid assertions must be delayed by one clock + // cycle. + // + // Note: out_valid deassertions must not be delayed or + // the FIFO will underflow. + // -------------------------------------------------- + assign in_ready = !full; + assign internal_out_ready = out_ready || !out_valid; + + generate if (EMPTY_LATENCY > 1) begin : gen_blk14 + always @(posedge clk or posedge reset) begin + if (reset) + internal_out_valid <= 0; + else begin + internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; + + if (read) begin + if (incremented_rd_ptr == wr_ptr) + internal_out_valid <= 1'b0; + end + end + end + end else begin : gen_blk14_else + always @* begin + internal_out_valid = !empty & ok_to_forward; + end + end + endgenerate + + // -------------------------------------------------- + // Single Output Pipeline Stage + // + // This output pipeline stage is enabled if the FIFO's + // empty latency is set to 3 (default). It is disabled + // for all other allowed latencies. + // + // Reason: The memory outputs are unregistered, so we have to + // register the output or fmax will drop if combinatorial + // logic is present on the output datapath. + // + // Q: The Avalon-ST spec says that I have to register my outputs + // But isn't the memory counted as a register? + // A: The path from the address lookup to the memory output is + // slow. Registering the memory outputs is a good idea. + // + // The registers get packed into the memory by the fitter + // which means minimal resources are consumed (the result + // is a altsyncram with registered outputs, available on + // all modern Altera devices). + // + // This output stage acts as an extra slot in the FIFO, + // and complicates the fill level. + // -------------------------------------------------- + generate if (EMPTY_LATENCY == 3) begin : gen_blk15 + always @(posedge clk or posedge reset) begin + if (reset) begin + out_valid <= 0; + out_payload <= 0; + end + else begin + if (internal_out_ready) begin + out_valid <= internal_out_valid & ok_to_forward; + out_payload <= internal_out_payload; + end + end + end + end + else begin : gen_blk15_else + always @* begin + out_valid = internal_out_valid; + out_payload = internal_out_payload; + end + end + endgenerate + + // -------------------------------------------------- + // Fill Level + // + // The fill level is calculated from the next write + // and read pointers to avoid unnecessary latency + // and logic. + // + // However, if the store-and-forward mode of the FIFO + // is enabled, the fill level is an up-down counter + // for fmax optimization reasons. + // + // If the output pipeline is enabled, the fill level + // must account for it, or we'll always be off by one. + // This may, or may not be important depending on the + // application. + // + // For now, we'll always calculate the exact fill level + // at the cost of an extra adder when the output stage + // is enabled. + // -------------------------------------------------- + generate if (USE_FILL_LEVEL) begin : gen_blk16 + wire [31:0] depth32; + assign depth32 = DEPTH; + + if (USE_STORE_FORWARD) begin + + reg [ADDR_WIDTH : 0] curr_packet_len_less_one; + + // -------------------------------------------------- + // We only drop on endofpacket. As long as we don't add to the fill + // level on the dropped endofpacket cycle, we can simply subtract + // (packet length - 1) from the fill level for dropped packets. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + curr_packet_len_less_one <= 0; + end else begin + if (write) begin + curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1; + if (in_endofpacket) + curr_packet_len_less_one <= 0; + end + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + fifo_fill_level <= 0; + end else if (drop_on_error) begin + fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one; + if (read) + fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1; + end else if (write && !read) begin + fifo_fill_level <= fifo_fill_level + 1'b1; + end else if (read && !write) begin + fifo_fill_level <= fifo_fill_level - 1'b1; + end + end + + end else begin + + always @(posedge clk or posedge reset) begin + if (reset) + fifo_fill_level <= 0; + else if (next_full & !drop_on_error) + fifo_fill_level <= depth32[ADDR_WIDTH:0]; + else begin + fifo_fill_level[ADDR_WIDTH] <= 1'b0; + fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; + end + end + + end + + always @* begin + fill_level = fifo_fill_level; + + if (EMPTY_LATENCY == 3) + fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; + end + end + else begin : gen_blk16_else + always @* begin + fill_level = 0; + end + end + endgenerate + + generate if (USE_ALMOST_FULL_IF) begin : gen_blk17 + assign almost_full_data = (fill_level >= almost_full_threshold); + end + else + assign almost_full_data = 0; + endgenerate + + generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18 + assign almost_empty_data = (fill_level <= almost_empty_threshold); + end + else + assign almost_empty_data = 0; + endgenerate + + // -------------------------------------------------- + // Avalon-MM Status & Control Connection Point + // + // Register map: + // + // | Addr | RW | 31 - 0 | + // | 0 | R | Fill level | + // + // The registering of this connection point means + // that there is a cycle of latency between + // reads/writes and the updating of the fill level. + // -------------------------------------------------- + generate if (USE_STORE_FORWARD) begin : gen_blk19 + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + cut_through_threshold <= 0; + drop_on_error_en <= 0; + csr_readdata <= 0; + pkt_mode <= 1'b1; + end + else begin + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 5) + csr_readdata <= {31'b0, drop_on_error_en}; + else if (csr_address == 4) + csr_readdata <= {8'b0, cut_through_threshold}; + else if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + else if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + else if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + end + else if (csr_write) begin + if(csr_address == 3'b101) + drop_on_error_en <= csr_writedata[0]; + else if(csr_address == 3'b100) begin + cut_through_threshold <= csr_writedata[23:0]; + pkt_mode <= (csr_writedata[23:0] == 0); + end + else if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + else if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + end + end + end + end + else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1 + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + csr_readdata <= 0; + end + else begin + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + else if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + else if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + end + else if (csr_write) begin + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + else if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + end + end + end + end + else begin : gen_blk19_else2 + always @(posedge clk or posedge reset) begin + if (reset) begin + csr_readdata <= 0; + end + else if (csr_read) begin + csr_readdata <= 0; + + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + end + end + end + endgenerate + + // -------------------------------------------------- + // Store and forward logic + // -------------------------------------------------- + // if the fifo gets full before the entire packet or the + // cut-threshold condition is met then start sending out + // data in order to avoid dead-lock situation + + generate if (USE_STORE_FORWARD) begin : gen_blk20 + assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; + assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); + assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : + ~wait_for_threshold) | fifo_too_small_r; + assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; + assign in_pkt_start = in_valid & in_ready & in_startofpacket; + assign in_pkt_error = in_valid & in_ready & |in_error; + assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; + assign out_pkt_leave = out_valid & out_ready & out_endofpacket; + assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; + + // count packets coming and going into the fifo + always @(posedge clk or posedge reset) begin + if (reset) begin + pkt_cnt <= 0; + pkt_has_started <= 0; + sop_has_left_fifo <= 0; + fifo_too_small_r <= 0; + pkt_cnt_eq_zero <= 1'b1; + pkt_cnt_eq_one <= 1'b0; + fifo_fill_level_lt_cut_through_threshold <= 1'b1; + end + else begin + fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; + fifo_too_small_r <= fifo_too_small; + + if( in_pkt_eop_arrive ) + sop_has_left_fifo <= 1'b0; + else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) + sop_has_left_fifo <= 1'b1; + + if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin + pkt_cnt <= pkt_cnt + 1'b1; + pkt_cnt_eq_zero <= 0; + if (pkt_cnt == 0) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin + pkt_cnt <= pkt_cnt - 1'b1; + if (pkt_cnt == 1) + pkt_cnt_eq_zero <= 1'b1; + else + pkt_cnt_eq_zero <= 1'b0; + if (pkt_cnt == 2) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + + if (in_pkt_start) + pkt_has_started <= 1'b1; + else if (in_pkt_eop_arrive) + pkt_has_started <= 1'b0; + end + end + + // drop on error logic + always @(posedge clk or posedge reset) begin + if (reset) begin + sop_ptr <= 0; + error_in_pkt <= 0; + end + else begin + // save the location of the SOP + if ( in_pkt_start ) + sop_ptr <= wr_ptr; + + // remember if error in pkt + // log error only if packet has already started + if (in_pkt_eop_arrive) + error_in_pkt <= 1'b0; + else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) + error_in_pkt <= 1'b1; + end + end + + assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & + ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); + + assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr; + + end + else begin : gen_blk20_else + assign ok_to_forward = 1'b1; + assign drop_on_error = 1'b0; + if (ADDR_WIDTH <= 1) + assign curr_sop_ptr = 1'b0; + else + assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }}; + end + endgenerate + + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + reg[31:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i[30:0] << 1; + end + end + endfunction + +endmodule diff --git a/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_controller_hpfir.vhd b/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_controller_hpfir.vhd new file mode 100644 index 0000000..ce5b599 --- /dev/null +++ b/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_controller_hpfir.vhd @@ -0,0 +1,88 @@ +-- (C) 2001-2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files from any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License Subscription +-- Agreement, Intel FPGA IP License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +------------------------------------------------------------------------- +------------------------------------------------------------------------- +-- +-- $Revision: #1 $ +-- $Date: 2009/07/29 $ +-- Author : Boon Hong Oh +-- +-- Project : Avalon Streaming Wrapper for HP FIR +-- +-- Description : +-- +-- This file is the Interface controller for the Avalon Streaming Wrapper. +-- The control signals between sink, core, and source modules are communicated +-- via the controller. The stall output is used as the core enable signal in +-- the wrapper. +-- +-- ALTERA Confidential and Proprietary +-- Copyright 2006 (c) Altera Corporation +-- All rights reserved +-- +------------------------------------------------------------------------- +------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + + +entity auk_dspip_avalon_streaming_controller_hpfir is + port( + clk : in std_logic; + --clk_en : in std_logic := '1'; + reset_n : in std_logic; + --ready : in std_logic; + sink_packet_error : in std_logic_vector (1 downto 0); + --sink_stall : in std_logic; + source_stall : in std_logic; + valid : in std_logic; + reset_design : out std_logic; + sink_ready_ctrl : out std_logic; + source_packet_error : out std_logic_vector (1 downto 0) := (others => '0'); + source_valid_ctrl : out std_logic; + stall : out std_logic + ); + +-- Declarations + +end auk_dspip_avalon_streaming_controller_hpfir; + +-- hds interface_end + +architecture struct of auk_dspip_avalon_streaming_controller_hpfir is + +-- signal stall_int : std_logic; +-- signal stall_reg : std_logic; + +-- attribute maxfan : integer; +-- attribute maxfan of stall_reg : signal is 500; + +begin + + reset_design <= not reset_n; + + --should not stop sending data to source module when the sink module is stalled + --should only stop sending when the source module is stalled + + --Disable the FIR core when backpressure + stall <= source_stall; + source_valid_ctrl <= valid; + + -- Sink FIFO and FIR core are disabled at the same time + sink_ready_ctrl <= not(source_stall); + + source_packet_error <= sink_packet_error; + +end struct; diff --git a/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_sink_hpfir.vhd b/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_sink_hpfir.vhd new file mode 100644 index 0000000..082bf84 --- /dev/null +++ b/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_sink_hpfir.vhd @@ -0,0 +1,545 @@ +-- (C) 2001-2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files from any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License Subscription +-- Agreement, Intel FPGA IP License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +------------------------------------------------------------------------- +------------------------------------------------------------------------- +-- +-- Revision Control Information +-- +-- $Revision: #1 $ +-- $Date: 2009/07/29 $ +-- Author : Boon Hong Oh +-- +-- Project : Atlantic II Sink Interface with ready_latency=0 +-- +-- Description : +-- +-- This interface is capable of handling single or multi channel streams as +-- well as blocks of data. The at_sink_sop and at_sink_eop must be fed as +-- described in the Atlantic II specification. The at_sink_error input is a 2- +-- bit signal that complies with the PFC error format (by Kent Orthner). The +-- error checking is extensively done, however the resulting information is +-- still mapped on the available 3 error states as shown below. +-- 00: no error +-- 01: missing sop +-- 10: missing eop +-- 11: unexpected eop +-- other types of errors also marked as 11. +-- +-- ALTERA Confidential and Proprietary +-- Copyright 2006 (c) Altera Corporation +-- All rights reserved +-- +------------------------------------------------------------------------- +------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +--use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +use work.auk_dspip_lib_pkg_hpfir.all; +use work.auk_dspip_math_pkg_hpfir.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity auk_dspip_avalon_streaming_sink_hpfir is + + generic( + WIDTH_g : integer := 24; -- DATA_PORT_COUNT * DATA_WIDTH + DATA_WIDTH : integer := 8; + DATA_PORT_COUNT : integer := 3; + PACKET_SIZE_g : natural := 2 + --FIFO_DEPTH_g : natural := 8 --if PFC mode is selected, this generic + --is used for passing the poly_factor. + --MIN_DATA_COUNT_g : natural := 2; + --PFC_MODE_g : boolean := false; + --SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than + -- reading value from fifo + --FAMILY_g : string := "Stratix II"; + --MEM_TYPE_g : string := "Auto" + ); + port( + clk : in std_logic; + reset_n : in std_logic; + ----------------- DESIGN SIDE SIGNALS + data : out std_logic_vector(WIDTH_g-1 downto 0); + data_valid : out std_logic_vector(0 downto 0); + + sink_ready_ctrl : in std_logic; --the controller will tell + --the interface whether + --new input can be accepted. + --sink_stall : out std_logic; --needs to stall the design + --if no new data is coming + packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only. + --when any of these doesn't behave as + --expected, the error is flagged. + --send_sop : out std_logic; -- transmit SOP signal to the design. + -- It only transmits the legal SOP. + --send_eop : out std_logic; -- transmit EOP signal to the design. + -- It only transmits the legal EOP. + ----------------- ATLANTIC SIDE SIGNALS + at_sink_ready : out std_logic; --it will be '1' whenever the + --sink_ready_ctrl signal is high. + at_sink_valid : in std_logic; + at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0); + at_sink_sop : in std_logic := '0'; + at_sink_eop : in std_logic := '0'; + at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates + --that there is an error in the packet. + + ); + +end auk_dspip_avalon_streaming_sink_hpfir; + +-- hds interface_end +architecture rtl of auk_dspip_avalon_streaming_sink_hpfir is + + type STATE_TYPE_t is (start, stall, run1, st_err, end1); -- stall,run_once,wait1, + type OUT_STATE_TYPE_t is (normal, empty_and_not_ready, empty_and_ready); + constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g); + + signal sink_state : STATE_TYPE_t; + signal sink_next_state : STATE_TYPE_t; + signal reset_count : std_logic; + signal count_enable : std_logic; + signal count : unsigned(LOG2PACKET_SIZE_c -1 downto 0); + signal count_finished : boolean; + signal at_sink_error_int : std_logic; + signal packet_error_int : std_logic_vector (1 downto 0); + signal packet_error_s : std_logic_vector(1 downto 0); + + signal at_sink_ready_s : std_logic; + --signal reset : std_logic; + signal max_reached : boolean; -- flag to show counter has reached max value + +-- component altera_avalon_sc_fifo is +-- generic( +-- SYMBOLS_PER_BEAT : integer := 1; +-- BITS_PER_SYMBOL : integer := 8; +-- FIFO_DEPTH : integer := 16; +-- CHANNEL_WIDTH : integer := 0; +-- ERROR_WIDTH : integer := 0; +-- USE_PACKETS : integer := 0 +-- ); +-- port ( +-- -- inputs: +-- signal clk : IN STD_LOGIC; +-- signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0); +-- signal in_valid : IN STD_LOGIC; +-- signal in_startofpacket : IN STD_LOGIC; +-- signal in_endofpacket : IN STD_LOGIC; +-- signal out_ready : IN STD_LOGIC; +-- signal reset : IN STD_LOGIC; +-- +-- signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0); +-- signal in_error : IN STD_LOGIC_VECTOR (0 DOWNTO 0); +-- signal in_channel : IN STD_LOGIC_VECTOR (0 DOWNTO 0); +-- +-- signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0); +-- signal csr_write : IN STD_LOGIC; +-- signal csr_read : IN STD_LOGIC; +-- signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); +-- +-- -- outputs: +-- signal in_ready : OUT STD_LOGIC; +-- signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0); +-- signal out_valid : OUT STD_LOGIC; +-- +-- signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0); +-- signal out_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); +-- signal out_channel : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) +-- ); +-- end component altera_avalon_sc_fifo; +begin + + valid_generate_single : if PACKET_SIZE_g = 1 generate + signal packet_error0 : std_logic; + begin + at_sink_error_int <= at_sink_error(0) when at_sink_valid = '1' else + '0'; + + packet_error_int <= '0' & packet_error0; + + packet_error0 <= '0' when at_sink_error_int = '0' and sink_next_state /= st_err else + '1'; + + sink_comb_update_1 : process (sink_state, at_sink_valid, at_sink_error_int, at_sink_ready_s) + begin -- process sink_comb_update_1 + case sink_state is + when start => + --fifo_wrreq <= '0'; + if at_sink_error_int = '1' then + sink_next_state <= st_err; + else + if at_sink_ready_s = '0' and at_sink_valid = '0' then + sink_next_state <= start; + elsif at_sink_ready_s = '0' and at_sink_valid = '1' then + sink_next_state <= start; + elsif at_sink_ready_s = '1' and at_sink_valid = '0' then + sink_next_state <= stall; + elsif at_sink_ready_s = '1' and at_sink_valid = '1' then + sink_next_state <= run1; + else + sink_next_state <= st_err; + end if; + end if; + when stall => + --fifo_wrreq <= '0'; + if at_sink_error_int = '1' then + sink_next_state <= st_err; + else + if at_sink_ready_s = '0' and at_sink_valid = '0' then + sink_next_state <= start; + elsif at_sink_ready_s = '0' and at_sink_valid = '1' then + sink_next_state <= start; + elsif at_sink_ready_s = '1' and at_sink_valid = '0' then + sink_next_state <= stall; + elsif at_sink_ready_s = '1' and at_sink_valid = '1' then + sink_next_state <= run1; + else + sink_next_state <= st_err; + end if; + end if; + + when run1 => + --fifo_wrreq <= '1'; + if at_sink_error_int = '1' then + sink_next_state <= st_err; + else + if at_sink_ready_s = '0' and at_sink_valid = '0' then + sink_next_state <= start; + elsif at_sink_ready_s = '0' and at_sink_valid = '1' then + sink_next_state <= start; + elsif at_sink_ready_s = '1' and at_sink_valid = '0' then + sink_next_state <= stall; + elsif at_sink_ready_s = '1' and at_sink_valid = '1' then + sink_next_state <= run1; + else + sink_next_state <= st_err; + end if; + end if; + + when st_err => + --fifo_wrreq <= '0'; + if at_sink_error_int = '1' then + sink_next_state <= st_err; + else + if at_sink_ready_s = '0' and at_sink_valid = '0' then + sink_next_state <= start; + elsif at_sink_ready_s = '0' and at_sink_valid = '1' then + sink_next_state <= start; + elsif at_sink_ready_s = '1' and at_sink_valid = '0' then + sink_next_state <= stall; + elsif at_sink_ready_s = '1' and at_sink_valid = '1' then + sink_next_state <= run1; + else + sink_next_state <= st_err; + end if; + end if; + + when others => + sink_next_state <= st_err; + --fifo_wrreq <= '0'; + end case; + end process sink_comb_update_1; + end generate valid_generate_single; + + + valid_generate_mult : if PACKET_SIZE_g > 1 generate + + at_sink_error_int <= at_sink_error(1) or at_sink_error(0) when at_sink_valid = '1' else + '0'; + + count_enable <= '1' when (sink_next_state = run1 or sink_next_state = end1) else -- + --or sink_next_state = run_once) else + '0'; + reset_count <= '1' when sink_next_state = st_err else + '0'; + + sink_comb_update_2 : process (sink_state, at_sink_ready_s, at_sink_valid, + at_sink_error, at_sink_error_int, at_sink_sop, + at_sink_eop, count, count_finished) + begin -- process sink_comb_update_2 + case sink_state is + when start => + --fifo_wrreq <= '0'; + + if at_sink_error_int = '1' then + sink_next_state <= st_err; + packet_error_int <= at_sink_error; + else + if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then + sink_next_state <= run1; + packet_error_int <= "00"; + elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then + sink_next_state <= st_err; + packet_error_int <= "01"; + else + sink_next_state <= start; + packet_error_int <= "00"; + end if; + end if; + + when run1 => + --fifo_wrreq <= '1'; + + if at_sink_error_int = '1' then + sink_next_state <= st_err; + packet_error_int <= at_sink_error; + elsif at_sink_sop = '1' and at_sink_valid = '1' then + sink_next_state <= st_err; + packet_error_int <= "01"; + elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then + sink_next_state <= st_err; + packet_error_int <= "11"; + else + if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then + sink_next_state <= run1; + packet_error_int <= "00"; + elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then + sink_next_state <= end1; + packet_error_int <= "00"; + elsif (count_finished = true and at_sink_valid = '0' and at_sink_ready_s = '1') or + (at_sink_valid = '0' and at_sink_ready_s = '1') then + sink_next_state <= stall; + packet_error_int <= "00"; + elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then + sink_next_state <= stall; --wait1; + packet_error_int <= "00"; + elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then + sink_next_state <= st_err; + packet_error_int <= "10"; + else + sink_next_state <= st_err; + packet_error_int <= "11"; + end if; + end if; + when stall => + --fifo_wrreq <= '0'; + + if at_sink_error_int = '1' then + sink_next_state <= st_err; + packet_error_int <= at_sink_error; + elsif at_sink_sop = '1' and at_sink_valid = '1' then + sink_next_state <= st_err; + packet_error_int <= "01"; + elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then + sink_next_state <= st_err; + packet_error_int <= "11"; + else + if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then --and at_sink_ready_int = '1' then + sink_next_state <= run1; + packet_error_int <= "00"; + elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then + sink_next_state <= end1; + packet_error_int <= "00"; + elsif (count_finished = true and at_sink_valid = '0') or -- and at_sink_ready_s = '1') or + (at_sink_valid = '0' and at_sink_ready_s = '1') then + sink_next_state <= stall; + packet_error_int <= "00"; + elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then + sink_next_state <= stall; --wait1; + packet_error_int <= "00"; + elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then + sink_next_state <= st_err; + packet_error_int <= "10"; + else + sink_next_state <= st_err; + packet_error_int <= "11"; + end if; + end if; + + when end1 => + --fifo_wrreq <= '1'; + + if at_sink_error_int = '1' then + sink_next_state <= st_err; + packet_error_int <= at_sink_error; + else + if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then + sink_next_state <= run1; + packet_error_int <= "00"; + elsif (at_sink_valid = '1' and at_sink_sop = '0') then + sink_next_state <= st_err; + packet_error_int <= "01"; + else + sink_next_state <= start; + packet_error_int <= "00"; + end if; + end if; + when st_err => + --fifo_wrreq <= '0'; + if at_sink_error_int = '1' then + sink_next_state <= st_err; + packet_error_int <= at_sink_error; + else + if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then + sink_next_state <= run1; + packet_error_int <= "00"; + elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then + sink_next_state <= st_err; + packet_error_int <= "01"; + else + sink_next_state <= start; + packet_error_int <= "00"; + end if; + end if; + when others => null; + end case; + end process sink_comb_update_2; + + + counter : process (clk, reset_n) + begin -- process counter + if reset_n = '0' then + count <= (others => '0'); + max_reached <= false; + elsif clk'event and clk = '1' then -- rising clock edge + if reset_count = '1' then + count <= (others => '0'); + else + if count_enable = '1' then + if count = PACKET_SIZE_g-2 then + max_reached <= true; + else + max_reached <= false; + end if; + + if max_reached = false then + count <= count + 1; + else + count <= (others => '0'); + end if; + end if; + end if; + end if; + end process counter; + + count_finished <= max_reached; + + end generate valid_generate_mult; + + sink_input_update : process (clk, reset_n) + begin -- process + if reset_n = '0' then + sink_state <= start; + elsif clk'event and clk = '1' then + sink_state <= sink_next_state; + end if; + end process sink_input_update; + +-- sink_output_update : process (clk, reset_n) +-- begin -- process +-- if reset_n = '0' then +-- sink_out_state <= normal; +-- elsif clk'event and clk = '1' then +-- sink_out_state <= sink_out_next_state; +-- end if; +-- end process sink_output_update; + + error_register : process (clk, reset_n) + begin -- process + if reset_n = '0' then + packet_error_s <= "00"; + elsif clk'event and clk = '1' then + packet_error_s <= packet_error_int; + end if; + end process; + + packet_error <= packet_error_s; + + ----------------------------------------------------------------------------- + -- This was included because the vho simulations of fifo produce 'X' in + -- reset whcih means that for the FFT, alll outputs go to X when sop = X + ----------------------------------------------------------------------------- + --gen_calc_sop: if SOP_EOP_CALC_g = true generate +-- +-- -- generate sop and eop separate +-- out_cnt_p : process (clk, reset) +-- begin -- process out_cnt_p +-- if reset = '1' then +-- fifo_rdreq_d <= '0'; +-- out_cnt <= 0; +-- elsif rising_edge(clk) then +-- fifo_rdreq_d <= fifo_rdreq; +-- if fifo_rdreq = '1' then +-- if out_cnt < PACKET_SIZE_g - 1 then +-- out_cnt <= out_cnt + 1; +-- else +-- out_cnt <= 0; +-- end if; +-- end if; +-- end if; +-- end process out_cnt_p; +-- +-- send_sop_eop_p : process (clk, reset) +-- begin -- process send_sop_eop_p +-- if reset = '1' then +-- send_sop_s <= '0'; +-- send_eop_s <= '0'; +-- elsif rising_edge(clk) then +-- if fifo_rdreq = '1' and sink_ready_ctrl = '1' then +-- send_sop_s <= '0'; +-- send_eop_s <= '0'; +-- if out_cnt = 0 then +-- send_sop_s <= '1'; +-- end if; +-- if out_cnt = PACKET_SIZE_g - 1 then +-- send_eop_s <= '1'; +-- end if; +-- end if; +-- end if; +-- end process send_sop_eop_p; +-- +-- end generate gen_calc_sop; + + + + --reset <= not reset_n; + at_sink_ready <= at_sink_ready_s; + at_sink_ready_s <= sink_ready_ctrl; + data <= at_sink_data; + data_valid(0) <= at_sink_valid; + +-- sink_scfifo : altera_avalon_sc_fifo +-- generic map ( +-- SYMBOLS_PER_BEAT => DATA_PORT_COUNT, +-- BITS_PER_SYMBOL => DATA_WIDTH, +-- FIFO_DEPTH => FIFO_DEPTH_g, +-- CHANNEL_WIDTH => 0, +-- ERROR_WIDTH => 0, +-- USE_PACKETS => 0) +-- port map ( +-- clk => clk, +-- reset => reset, +-- in_ready => at_sink_ready_s, +-- in_data => at_sink_data, +-- in_valid => at_sink_valid, +-- in_startofpacket => '0', +-- in_endofpacket => '0', +-- out_ready => sink_ready_ctrl, +-- out_data => data, +-- out_valid => data_valid(0), +-- in_empty => (others => '0'), +-- in_error => (others => '0'), +-- in_channel => (others => '0'), +-- csr_address => (others => '0'), +-- csr_write => '0', +-- csr_read => '0', +-- csr_writedata => (others => '0'), +-- out_empty => open, +-- out_error => open, +-- out_channel => open); + +end rtl; diff --git a/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_source_hpfir.vhd b/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_source_hpfir.vhd new file mode 100644 index 0000000..ce8fee4 --- /dev/null +++ b/ld3/dds_vhdl/fir/auk_dspip_avalon_streaming_source_hpfir.vhd @@ -0,0 +1,467 @@ +-- (C) 2001-2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files from any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License Subscription +-- Agreement, Intel FPGA IP License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +------------------------------------------------------------------------- +------------------------------------------------------------------------- +-- +-- Revision Control Information +-- +-- $Revision: #1 $ +-- $Date: 2009/07/29 $ +-- Author : Boon Hong Oh +-- +-- Project : Avalon_streaming II Source Interface with ready_latency=0 +-- +-- Description : +-- +-- This interface is capable of handling single or multi channel streams as +-- well as blocks of data. The at_source_sop and at_source_eop are generated as +-- described in the Avalon_streaming II specification. The at_source_error output is a 2- +-- bit signal that complies with the PFC error format (by Kent Orthner). +-- +-- 00: no error +-- 01: missing sop +-- 10: missing eop +-- 11: unexpected eop +-- other types of errors also marked as 11. Any error signal is accompanied +-- by at_sink_eop flagged high. +-- +-- When packet_size is greater than one, this interface expects the main design +-- to supply the count of data starting from 1 to the packet_size. When it +-- receives the valid flag together with the data_count=1, it starts pumping +-- out data by flagging the at_source_sop and at_source_valid both high. +-- +-- When the data_count=packet_size, the at_source_eop is flagged high together +-- with at_source_valid. THERE IS NO ERROR CHECKING FOR THE data_count signal. +-- +-- If the receiver is not ready to accept any data, the interface flags the source_ +-- stall signal high to tell the design to stall. It is the designers +-- responsibility to use this signal properly. In some design, the stall signal +-- needs to stall all of the design so that no new data can be accepted (as in +-- FIR), in other cases (i.e. a FIFO built on a dual port RAM),the input can +-- still accept new data although it cannot send any output. +-- +-- ALTERA Confidential and Proprietary +-- Copyright 2006 (c) Altera Corporation +-- All rights reserved +-- +------------------------------------------------------------------------- +------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +--use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +use work.auk_dspip_math_pkg_hpfir.all; + +entity auk_dspip_avalon_streaming_source_hpfir is + generic( + WIDTH_g : integer := 8; -- DATA_PORT_COUNT * DATA_WIDTH + DATA_WIDTH : integer := 8; + DATA_PORT_COUNT : integer := 1; + PACKET_SIZE_g : natural := 2; + FIFO_DEPTH_g : natural := 0; + HAVE_COUNTER_g : boolean := false; + COUNTER_LIMIT_g : natural := 4; + --MULTI_CHANNEL_g : boolean := true; + USE_PACKETS : integer := 1; + --FAMILY_g : string := "Stratix II"; + --MEM_TYPE_g : string := "Auto"; + ENABLE_BACKPRESSURE_g : boolean := true + ); + port( + clk : in std_logic; + reset_n : in std_logic; + ----------------- DESIGN SIDE SIGNALS + data_in : in std_logic_vector (WIDTH_g-1 downto 0); + data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0'); + source_valid_ctrl : in std_logic; + source_stall : out std_logic; + packet_error : in std_logic_vector (1 downto 0); + ----------------- AVALON_STREAMING SIDE SIGNALS + at_source_ready : in std_logic; + at_source_valid : out std_logic; + at_source_data : out std_logic_vector (WIDTH_g-1 downto 0); + at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0); + at_source_error : out std_logic_vector (1 downto 0); + at_source_sop : out std_logic; + at_source_eop : out std_logic + ); + +-- Declarations + +end auk_dspip_avalon_streaming_source_hpfir; + +-- hds interface_end +architecture rtl of auk_dspip_avalon_streaming_source_hpfir is + + --constant FIFO_HINT_c : string := "RAM_BLOCK_TYPE="& MEM_TYPE_g; + constant FIFO_DEPTH_c : natural := FIFO_DEPTH_g; + constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g); + constant MIN_DATA_COUNT_g : natural := 2; + type STATE_TYPE_t is (start, sop, run1, st_err, end1); --wait1, stall, + signal source_state : STATE_TYPE_t; + signal source_next_state : STATE_TYPE_t; + signal packet_error0 : std_logic; + signal at_source_error_int : std_logic_vector(1 downto 0); + signal at_source_sop_int : std_logic := '0'; + signal at_source_eop_int : std_logic := '0'; + signal count_finished : boolean := false; + signal count_started : boolean := false; + signal at_source_valid_s : std_logic; + + signal data_valid : std_logic; + signal data_out : std_logic_vector(WIDTH_g-1 downto 0); + signal fifo_count : std_logic_vector(DATA_PORT_COUNT*log2_ceil(FIFO_DEPTH_g)-1 downto 0); + signal fifo_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0); -- multichan, multiinout + signal fifo_alm_empty : std_logic_vector(DATA_PORT_COUNT-1 downto 0); + signal fifo_alm_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0); + signal fifo_full : std_logic_vector(DATA_PORT_COUNT-1 downto 0); + signal clear_fifo : std_logic; + signal fifo_rdreq : std_logic; + signal fifo_rdreq_d : std_logic; + signal fifo_wrreq : std_logic; + signal fifo_empty_d : std_logic; + signal reset_design_int : std_logic; + signal channel_out : std_logic_vector(log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0'); + + signal fifo_sop_in : std_logic := '0'; + signal fifo_eop_in : std_logic := '0'; + signal fifo_error_in : std_logic_vector(1 downto 0); + signal at_source_sop_s : std_logic := '0'; + signal at_source_eop_s : std_logic := '0'; + signal at_source_error_s : std_logic_vector(1 downto 0); + signal in_ready : std_logic; + + component altera_avalon_sc_fifo is + generic( + SYMBOLS_PER_BEAT : integer := 1; + BITS_PER_SYMBOL : integer := 8; + FIFO_DEPTH : integer := 16; + CHANNEL_WIDTH : integer := 2; + ERROR_WIDTH : integer := 2; + --EMPTY_LATENCY : integer := 0; + USE_PACKETS : integer := 0 + ); + port ( + -- inputs: + signal clk : IN STD_LOGIC; + signal in_channel : IN STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0); + signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0); + signal in_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + signal in_endofpacket : IN STD_LOGIC; + signal in_startofpacket : IN STD_LOGIC; + signal in_valid : IN STD_LOGIC; + signal out_ready : IN STD_LOGIC; + signal reset : IN STD_LOGIC; + + signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0); + + signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + signal csr_write : IN STD_LOGIC; + signal csr_read : IN STD_LOGIC; + signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + + -- outputs: + signal in_ready : OUT STD_LOGIC; + signal out_channel : OUT STD_LOGIC_VECTOR (log2_ceil_one(PACKET_SIZE_g)-1 DOWNTO 0); + signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0); + signal out_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + signal out_endofpacket : OUT STD_LOGIC; + signal out_startofpacket : OUT STD_LOGIC; + signal out_valid : OUT STD_LOGIC; + signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0) + ); + end component altera_avalon_sc_fifo; + +begin + single_channel : if USE_PACKETS = 0 generate + at_source_sop_int <= '0'; + at_source_eop_int <= '0'; + packet_error0 <= packet_error(0); + at_source_error_int(1) <= '0'; + at_source_error_int(0) <= packet_error0; + end generate single_channel; + + packet_multi : if USE_PACKETS = 1 generate + packet_error0 <= packet_error(1) or packet_error(0); + + counter_no : if HAVE_COUNTER_g = false generate + signal data_counter : unsigned(LOG2PACKET_SIZE_c-1 downto 0); + begin + count_finished <= true when data_counter = to_unsigned(PACKET_SIZE_g-1, LOG2PACKET_SIZE_c) else + false; + data_counter <= unsigned(data_count); + + count_started <= true when data_counter = 0 else + false; + end generate counter_no; + + counter_yes : if HAVE_COUNTER_g = true generate + signal data_counter : unsigned(log2_ceil(COUNTER_LIMIT_g)-1 downto 0); + begin + count_finished <= true when data_counter = to_unsigned(COUNTER_LIMIT_g-1, log2_ceil(COUNTER_LIMIT_g)) else + false; + count_started <= true when data_counter = 0 else + false; + + packet_counter : process (clk, reset_n) + begin -- process packet_counter + if reset_n = '0' then + data_counter <= (others => '0'); + elsif rising_edge(clk) then + if source_state = start and source_next_state = sop then + data_counter <= --(others => '0'); -- + data_counter +1; + elsif data_valid = '1' and at_source_ready = '1' and (data_counter < COUNTER_LIMIT_g-1) then + data_counter <= data_counter +1; + elsif count_finished = true then + data_counter <= (others => '0'); + end if; + end if; + end process packet_counter; + end generate counter_yes; + + source_comb_update : process (--at_source_ready, + count_finished, count_started, + packet_error, packet_error0, source_state, + --at_source_valid_s + in_ready, + source_valid_ctrl) + + begin -- process source_comb_update + + case source_state is + when start => + if packet_error0 = '1' then + source_next_state <= st_err; + at_source_error_int <= packet_error; + at_source_sop_int <= '0'; + at_source_eop_int <= '1'; + else + at_source_eop_int <= '0'; + at_source_error_int <= "00"; + if source_valid_ctrl = '1' and count_started = true then --and at_source_ready='1' then + source_next_state <= sop; + at_source_sop_int <= '1'; + else + source_next_state <= start; + at_source_sop_int <= '0'; + end if; + end if; + + when sop => + if packet_error0 = '1' then + source_next_state <= st_err; + at_source_error_int <= packet_error; + at_source_sop_int <= '0'; + at_source_eop_int <= '1'; + else + at_source_error_int <= "00"; + at_source_eop_int <= '0'; + --if source_valid_ctrl = '1' and at_source_ready = '1' and count_finished = false then + if source_valid_ctrl = '1' and in_ready = '1' and count_finished = false then + if PACKET_SIZE_g > 2 then + source_next_state <= run1; + else + source_next_state <= end1; + end if; + at_source_sop_int <= '0'; + --elsif (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or + elsif (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or + (source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and + source_next_state <= end1; + at_source_error_int <= "00"; + at_source_eop_int <= '1'; + at_source_sop_int <= '0'; + else + source_next_state <= sop; + at_source_sop_int <= '1'; + end if; + end if; + + when run1 => + at_source_sop_int <= '0'; + + if packet_error0 = '1' then + source_next_state <= st_err; + at_source_error_int <= packet_error; + at_source_eop_int <= '1'; + else + --if (at_source_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or + if (in_ready = '1' and source_valid_ctrl = '1' and count_finished = true) or + (source_valid_ctrl = '0' and count_finished = true) then --valid_ctrl_int = '1' and + source_next_state <= end1; + at_source_error_int <= "00"; + at_source_eop_int <= '1'; + else + source_next_state <= run1; + at_source_error_int <= "00"; + at_source_eop_int <= '0'; + end if; + end if; + + when end1 => + + if packet_error0 = '1' then + source_next_state <= st_err; + at_source_error_int <= packet_error; + at_source_sop_int <= '0'; + at_source_eop_int <= '1'; + else + at_source_error_int <= "00"; + --if source_valid_ctrl = '1' and count_started = true and at_source_ready = '1' then + if source_valid_ctrl = '1' and count_started = true and in_ready = '1' then + source_next_state <= sop; + at_source_sop_int <= '1'; + at_source_eop_int <= '0'; + --elsif source_valid_ctrl = '1' and at_source_ready = '1' then + elsif source_valid_ctrl = '1' and in_ready = '1' then + source_next_state <= start; + at_source_sop_int <= '0'; + at_source_eop_int <= '0'; + else + source_next_state <= end1; + at_source_sop_int <= '0'; + at_source_eop_int <= '1'; + end if; + end if; + + when st_err => + at_source_sop_int <= '0'; + at_source_eop_int <= '0'; + if packet_error0 = '1' then + source_next_state <= st_err; + at_source_error_int <= packet_error; + else + source_next_state <= start; + at_source_error_int <= "00"; + end if; + when others => + source_next_state <= st_err; + at_source_sop_int <= '0'; + at_source_eop_int <= '1'; + at_source_error_int <= "11"; + + end case; + end process source_comb_update; + + source_state_update : process (clk, reset_n) + begin -- process + if reset_n = '0' then + source_state <= start; + elsif clk'event and clk = '1' then + source_state <= source_next_state; + end if; + end process source_state_update; + end generate packet_multi; + + at_source_sop <= at_source_sop_s; + at_source_eop <= at_source_eop_s; + at_source_error <= at_source_error_s; + + channel_info_exists : if USE_PACKETS = 1 generate + at_source_channel <= channel_out; + end generate channel_info_exists; + + no_channel_info : if USE_PACKETS = 0 generate + at_source_channel <= (others => '0'); + end generate no_channel_info; + + at_source_data <= data_out; + at_source_valid <= data_valid; + + + backpressure_support: if ENABLE_BACKPRESSURE_g = true generate + reset_design_int <= not reset_n; + + --source_stall <= not(in_ready); + source_stall <= not(at_source_ready); + + fifo_sop_in <= '0' when USE_PACKETS = 0 else + at_source_sop_int; + + fifo_eop_in <= '0' when USE_PACKETS = 0 else + at_source_eop_int; + + fifo_error_in <= "00" when USE_PACKETS = 0 else + at_source_error_int; + + scfifo : altera_avalon_sc_fifo + generic map ( + SYMBOLS_PER_BEAT => DATA_PORT_COUNT, + BITS_PER_SYMBOL => DATA_WIDTH, + FIFO_DEPTH => FIFO_DEPTH_c, + CHANNEL_WIDTH => log2_ceil_one(PACKET_SIZE_g), + ERROR_WIDTH => 2, + --EMPTY_LATENCY => 1, + USE_PACKETS => USE_PACKETS) + port map ( + clk => clk, + reset => reset_design_int, + in_ready => in_ready, + --in_data => fifo_datain(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)), + in_data => data_in, + in_valid => source_valid_ctrl, + in_error => fifo_error_in, + in_channel => data_count, + in_startofpacket => fifo_sop_in, + in_endofpacket => fifo_eop_in, + + in_empty => (others => '0'), + csr_address => (others => '0'), + csr_write => '0', + csr_read => '0', + csr_writedata => (others => '0'), + out_ready => at_source_ready, + --out_data => fifo_dataout(((0*DATA_WIDTH)+DATA_WIDTH-1) downto (0*DATA_WIDTH)), + out_data => data_out, + out_valid => data_valid, + out_error => at_source_error_s, + out_channel => channel_out, + out_startofpacket => at_source_sop_s, + out_endofpacket => at_source_eop_s, + out_empty => open); + +end generate backpressure_support; + + +backpressure_no_support: if ENABLE_BACKPRESSURE_g = false generate + in_ready <= '1'; + source_stall <= '0'; + + output_registers : process (clk, reset_n) + begin + if reset_n = '0' then + channel_out <= (others => '0'); + data_out <= (others => '0'); + data_valid <= '0'; + at_source_error_s <= "00"; + at_source_sop_s <= '0'; + at_source_eop_s <= '0'; + elsif rising_edge(clk) then + channel_out <= data_count; + data_out <= data_in; + data_valid <= source_valid_ctrl; + at_source_error_s <= at_source_error_int; + at_source_sop_s <= at_source_sop_int; + at_source_eop_s <= at_source_eop_int; + end if; + end process output_registers; +end generate backpressure_no_support; + +end rtl; + diff --git a/ld3/dds_vhdl/fir/auk_dspip_lib_pkg_hpfir.vhd b/ld3/dds_vhdl/fir/auk_dspip_lib_pkg_hpfir.vhd new file mode 100644 index 0000000..7b72436 --- /dev/null +++ b/ld3/dds_vhdl/fir/auk_dspip_lib_pkg_hpfir.vhd @@ -0,0 +1,583 @@ +-- (C) 2001-2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files from any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License Subscription +-- Agreement, Intel FPGA IP License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Alex, 02-10-07, this package declaration results in error at built time on a new machine +-- +use work.auk_dspip_math_pkg_hpfir.all; + +package auk_dspip_lib_pkg_hpfir is +--Component names: +--auk_dspip_atlantic_sink +--auk_dspip_atlantic_source +--auk_dspip_interface_controller +--auk_dspip_avalon_streaming_controller_hpfir +--auk_dspip_avalon_streaming_controller_pe_fir_91 +--auk_dspip_avalon_streaming_sink_hpfir +--auk_dspip_avalon_streaming_source_hpfir +--auk_dspip_delay_fir_91 +--auk_dspip_fastadd_fir_91 +--auk_dspip_fastaddsub_fir_91 +--auk_dspip_pipelined_adder_fir_91 +--auk_dspip_fast_accumulator_fir_91 +--auk_dspip_fifo_pfc_fir_91 +--auk_dspip_fpcompiler_alufp +--auk_dspip_fpcompiler_aslf +--auk_dspip_fpcompiler_asrf +--auk_dspip_fpcompiler_castftox +--auk_dspip_fpcompiler_castxtof +--auk_dspip_fpcompiler_clzf +--auk_dspip_fpcompiler_mulfp +--auk_dspip_pfc_fir_91 +--auk_dspip_roundsat_fir_91 +component auk_dspip_atlantic_sink is + + generic( + WIDTH : integer := 16; + PACKET_SIZE : natural := 4; + log2packet_size : integer := 2 + ); + port( + clk : in std_logic; + reset_n : in std_logic; + ----------------- DESIGN SIDE SIGNALS + data_available : out std_logic; --goes high when new data is available + data : out std_logic_vector(WIDTH-1 downto 0); + sink_ready_ctrl : in std_logic; --the controller will tell + --the interface whether + --new input can be accepted. + sink_stall : out std_logic; --needs to stall the design + --if no new data is coming + packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only. + --when any of these doesn't behave as + --expected, the error is flagged. + send_sop : out std_logic; -- transmit SOP signal to the design. + -- It only transmits the legal SOP. + send_eop : out std_logic; -- transmit EOP signal to the design. + -- It only transmits the legal EOP. + ----------------- ATLANTIC SIDE SIGNALS + at_sink_ready : out std_logic; --it will be '1' whenever the + --sink_ready_ctrl signal is high. + at_sink_valid : in std_logic; + at_sink_data : in std_logic_vector(WIDTH-1 downto 0); + at_sink_sop : in std_logic := '0'; + at_sink_eop : in std_logic := '0'; + at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source + --that the SOP and EOP signals + --are not received as expected. + + ); + +end component auk_dspip_atlantic_sink; + +component auk_dspip_atlantic_source is + generic( + WIDTH : integer := 16; + packet_size : natural := 4; + LOG2packet_size : integer := 2; + multi_channel : BOOLEAN := TRUE + ); + port( + clk : in std_logic; + reset_n : in std_logic; + ----------------- DESIGN SIDE SIGNALS + data : in std_logic_vector (WIDTH-1 downto 0); + data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0'); + source_valid_ctrl : in std_logic; --the controller will tell + --the interface whether + --new input can be accepted. + source_stall : out std_logic; --needs to stall the design + --if no new data is coming + packet_error : in std_logic_vector (1 downto 0); + ----------------- ATLANTIC SIDE SIGNALS + at_source_ready : in std_logic; + at_source_valid : out std_logic; + at_source_data : out std_logic_vector (WIDTH-1 downto 0); + at_source_channel : out std_logic_vector (log2packet_size-1 downto 0); + at_source_error : out std_logic_vector (1 downto 0); + at_source_sop : out std_logic; + at_source_eop : out std_logic + ); + +-- Declarations + +end component auk_dspip_atlantic_source; + + +component auk_dspip_interface_controller IS + PORT( + clk : in std_logic; + reset : IN std_logic; + ready : in std_logic; + sink_packet_error : IN std_logic_vector (1 DOWNTO 0); + sink_stall : IN std_logic; + source_stall : IN std_logic; + valid : IN std_logic; + reset_design : OUT std_logic; + reset_n : OUT std_logic; + sink_ready_ctrl : OUT std_logic; + source_packet_error : OUT std_logic_vector (1 DOWNTO 0); + source_valid_ctrl : OUT std_logic; + stall : OUT std_logic + ); + +-- Declarations + +end component auk_dspip_interface_controller ; + + +component auk_dspip_avalon_streaming_controller_hpfir is + port( + clk : in std_logic; + --clk_en : in std_logic := '1'; + reset_n : in std_logic; + --ready : in std_logic; + sink_packet_error : in std_logic_vector (1 downto 0); + --sink_stall : in std_logic; + source_stall : in std_logic; + valid : in std_logic; + reset_design : out std_logic; + sink_ready_ctrl : out std_logic; + source_packet_error : out std_logic_vector (1 downto 0); + source_valid_ctrl : out std_logic; + stall : out std_logic + ); + +-- Declarations + +end component auk_dspip_avalon_streaming_controller_hpfir; + +component auk_dspip_avalon_streaming_controller_pe_fir_91 is + generic ( + FIFO_WIDTH_g : natural := 8; + ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core + FAMILY_g : string := "Stratix II"; + MEM_TYPE_g : string := "Auto" + ); + port( + clk : in std_logic; + clk_en : in std_logic := '1'; + reset_n : in std_logic; + ready : in std_logic; + sink_packet_error : in std_logic_vector (1 downto 0); + sink_stall : in std_logic; + source_stall : in std_logic; + valid : in std_logic; + reset_design : out std_logic; + sink_ready_ctrl : out std_logic; + source_packet_error : out std_logic_vector (1 downto 0); + source_valid_ctrl : out std_logic; + stall : out std_logic; + data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0); + data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0); + design_stall : out std_logic + ); + +-- Declarations + +end component auk_dspip_avalon_streaming_controller_pe_fir_91; + +component auk_dspip_avalon_streaming_sink_hpfir is + + generic( + WIDTH_g : integer := 16; + DATA_WIDTH : integer := 8; + DATA_PORT_COUNT : integer := 3; + PACKET_SIZE_g : natural := 4 + --FIFO_DEPTH_g : natural := 5 --if PFC mode is selected, this generic + --is used for passing the poly_factor. + --MIN_DATA_COUNT_g : natural := 2; + --PFC_MODE_g : boolean := false; + --SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than + -- reading value from fifo + --FAMILY_g : string := "Stratix II"; + --MEM_TYPE_g : string := "Auto" + ); + port( + clk : in std_logic; + reset_n : in std_logic; + ----------------- DESIGN SIDE SIGNALS + data : out std_logic_vector(WIDTH_g-1 downto 0); + data_valid : out std_logic_vector(0 downto 0); + sink_ready_ctrl : in std_logic; --the controller will tell + --the interface whether + --new input can be accepted. + --sink_stall : out std_logic; --needs to stall the design + --if no new data is coming + packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only. + --when any of these doesn't behave as + --expected, the error is flagged. + --send_sop : out std_logic; -- transmit SOP signal to the design. + -- It only transmits the legal SOP. + --send_eop : out std_logic; -- transmit EOP signal to the design. + -- It only transmits the legal EOP. + ----------------- ATLANTIC SIDE SIGNALS + at_sink_ready : out std_logic; --it will be '1' whenever the + --sink_ready_ctrl signal is high. + at_sink_valid : in std_logic; + at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0); + at_sink_sop : in std_logic := '0'; + at_sink_eop : in std_logic := '0'; + at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates + --that there is an error in the packet. + + ); + +end component auk_dspip_avalon_streaming_sink_hpfir; + +component auk_dspip_avalon_streaming_source_hpfir is + generic( + WIDTH_g : integer := 8; + DATA_WIDTH : integer := 8; + DATA_PORT_COUNT : integer := 1; + PACKET_SIZE_g : natural := 2; + FIFO_DEPTH_g : natural := 0; + HAVE_COUNTER_g : boolean := false; + COUNTER_LIMIT_g : natural := 4; + --MULTI_CHANNEL_g : boolean := true; + USE_PACKETS : integer := 1; + --FAMILY_g : string := "Stratix II"; + --MEM_TYPE_g : string := "Auto"; + ENABLE_BACKPRESSURE_g : boolean := true + ); + port( + clk : in std_logic; + reset_n : in std_logic; + ----------------- DESIGN SIDE SIGNALS + data_in : in std_logic_vector (WIDTH_g-1 downto 0); + data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0'); + source_valid_ctrl : in std_logic; + source_stall : out std_logic; + packet_error : in std_logic_vector (1 downto 0); + ----------------- AVALON_STREAMING SIDE SIGNALS + at_source_ready : in std_logic; + at_source_valid : out std_logic; + at_source_data : out std_logic_vector (WIDTH_g-1 downto 0); + at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0); + at_source_error : out std_logic_vector (1 downto 0); + at_source_sop : out std_logic; + at_source_eop : out std_logic + ); + +-- Declarations + +end component auk_dspip_avalon_streaming_source_hpfir; + +component auk_dspip_roundsat_hpfir is + generic ( + IN_WIDTH_g : natural := 8; -- i/p data width + REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed + REM_LSB_TYPE_g : string := "trunc"; -- trunc/round + REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed + REM_MSB_TYPE_g : string := "trunc" -- trunc/sat + ); + port ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); + valid : out std_logic; + dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0) + ); +end component auk_dspip_roundsat_hpfir; + +component auk_dspip_delay_fir_91 is + generic ( + WIDTH_g : natural := 8; -- data width + DELAY_g : natural := 8; + -- number of clock cycles the input + -- will be delayed by + MEMORY_TYPE_g : string := "AUTO"; + -- possible values are "m4k", "m512", + -- "register", "mram", "auto", + -- "lutram", "M9K", "M144K". + -- Any other string will be interpreted + -- as "auto" + REGISTER_FIRST_g : natural := 1; + -- if "1", the first delay is guaranteed + -- to be in registers + REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed + -- to be in registers + port ( + clk : in std_logic; + reset : in std_logic; + enable : in std_logic; -- global clock enable + datain : in std_logic_vector(WIDTH_g-1 downto 0); + dataout : out std_logic_vector(WIDTH_g-1 downto 0) + ); +end component auk_dspip_delay_fir_91; + + +component auk_dspip_fastadd_fir_91 is + generic ( + INWIDTH_g : natural := 18; + LABWIDTH_g : natural := 16); + -- width of lab in selected device ( 10 or 16 in Cyclone, + -- Cylone II, Stratix and Stratix II. Don't know + -- Stratix III yet. + port ( + datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); + datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + dataout : out std_logic_vector(INWIDTH_g downto 0)); +end component auk_dspip_fastadd_fir_91; + + +component auk_dspip_fastaddsub_fir_91 is + generic ( + INWIDTH_g : natural := 18; + LABWIDTH_g : natural := 16); + -- width of lab in selected device ( 10 or 16 in Cyclone, + -- Cylone II, Stratix and Stratix II. Don't know + -- Stratix III yet. + port ( + datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); + datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); + add_nsub : in std_logic; + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + dataout : out std_logic_vector(INWIDTH_g downto 0)); +end component auk_dspip_fastaddsub_fir_91; + + +component auk_dspip_pipelined_adder_fir_91 is + generic ( + INWIDTH_g : natural := 42; + -- width of lab in selected device ( 10 or 16 in Cyclone, + -- Cylone II, Stratix and Stratix II. + -- Alex : should I use 19 bits for Stratix III? + -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. + LABWIDTH_g : natural := 38); + port ( + datain1 : in std_logic_vector(INWIDTH_g-1 downto 0); + datain2 : in std_logic_vector(INWIDTH_g-1 downto 0); + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + dataout : out std_logic_vector(INWIDTH_g downto 0)); +end component auk_dspip_pipelined_adder_fir_91; + + +component auk_dspip_fast_accumulator_fir_91 is + generic ( + DATA_WIDTH_g : natural := 42; + -- width of lab in selected device ( 10 or 16 in Cyclone, + -- Cylone II, Stratix and Stratix II. + -- for Stratix III is 20 so labwidth should be set to 18. + -- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency. + LABWIDTH_g : natural := 38; + NUM_OF_CHANNELS_g : natural := 1; + ACCUM_OUT_WIDTH_g : natural := 48; + ACCUM_MEM_TYPE_g : string := "auto"); + port ( + reset : in std_logic; + clk : in std_logic; + enb : in std_logic; + add_to_zero : in std_logic; + datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); + datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0)); +end component auk_dspip_fast_accumulator_fir_91; + + +component auk_dspip_fifo_pfc_fir_91 is + generic ( + NUM_CHANNELS_g : integer := 5; + POLY_FACTOR_g : integer := 3; + DATA_WIDTH_g : integer := 16; + ALMOST_FULL_VALUE_g : integer := 2; + RAM_TYPE_g : string := "AUTO"; + CALCULATE_USED_WORDS_ONCE : boolean := true + ); + port ( + + datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); + datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0); + channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0); + used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0); + + wrreq : in std_logic; + rdreq : in std_logic; + almost_full : out std_logic; + empty : out std_logic; + sclr : in std_logic; + clk : in std_logic; + reset : in std_logic; + enable : in std_logic + ); +end component auk_dspip_fifo_pfc_fir_91; +component auk_dspip_fpcompiler_alufp is + port ( + sysclk : in std_logic; + reset : in std_logic; + enable : in std_logic; + addsub : in std_logic; + aa : in std_logic_vector (42 downto 1); + aasat, aazip : in std_logic; + bb : in std_logic_vector (42 downto 1); + bbsat, bbzip : in std_logic; + cc : out std_logic_vector (42 downto 1); + ccsat, cczip : out std_logic + ); +end component auk_dspip_fpcompiler_alufp; +component auk_dspip_fpcompiler_aslf is + port ( + inbus : in std_logic_vector (32 downto 1); + shift : in std_logic_vector (5 downto 1); + + outbus : out std_logic_vector (32 downto 1) + ); +end component auk_dspip_fpcompiler_aslf; +component auk_dspip_fpcompiler_asrf is + port ( + inbus : in std_logic_vector (32 downto 1); + shift : in std_logic_vector (5 downto 1); + + outbus : out std_logic_vector (32 downto 1) + ); +end component auk_dspip_fpcompiler_asrf; + +component auk_dspip_fpcompiler_castftox is + port ( + aa : in std_logic_vector (32 downto 1); + cc : out std_logic_vector (42 downto 1); + ccsat, cczip : out std_logic + ); +end component auk_dspip_fpcompiler_castftox; + +component auk_dspip_fpcompiler_castxtof is + port ( + sysclk : in std_logic; + reset : in std_logic; + enable : in std_logic; + aa : in std_logic_vector (42 downto 1); + aasat, aazip : in std_logic; + cc : out std_logic_vector (32 downto 1) + ); +end component auk_dspip_fpcompiler_castxtof; + +component auk_dspip_fpcompiler_clzf is + port ( + frac : in std_logic_vector (32 downto 1); + count : out std_logic_vector (5 downto 1) + ); +end component auk_dspip_fpcompiler_clzf; +component auk_dspip_fpcompiler_mulfp is + port ( + sysclk : in std_logic; + reset : in std_logic; + enable : in std_logic; + aa : in std_logic_vector (42 downto 1); + aasat, aazip : in std_logic; + bb : in std_logic_vector (42 downto 1); + bbsat, bbzip : in std_logic; + cc : out std_logic_vector (42 downto 1); + ccsat, cczip : out std_logic + ); +end component auk_dspip_fpcompiler_mulfp; + +component auk_dspip_pfc_fir_91 is + generic ( + NUM_CHANNELS_g : integer := 5; + POLY_FACTOR_g : integer := 3; + DATA_WIDTH_g : integer := 16; + RAM_TYPE_g : string := "AUTO" + ); + port ( + + datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0); + datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0); + channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0); + + in_valid : in std_logic; + out_valid : out std_logic; + clk : in std_logic; + reset : in std_logic; + enable : in std_logic + ); +end component auk_dspip_pfc_fir_91; + + +component auk_dspip_roundsat_fir_91 is + generic ( + IN_WIDTH_g : natural := 8; -- data width + OUT_WIDTH_g : natural := 8; -- data width + ROUNDING_TYPE_g : string := "TRUNCATE_LOW" + ); + + port ( + clk : in std_logic; + reset : in std_logic; + enable : in std_logic; -- global clock enable + datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); + dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0)); +end component auk_dspip_roundsat_fir_91; + +component auk_dspip_avalon_streaming_block_source_fir_91 is + generic ( + MAX_BLK_g : natural; + DATAWIDTH_g : natural); + port ( + clk : in std_logic; + reset : in std_logic; + in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); + in_valid : in std_logic; + source_stall : out std_logic; + in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); + source_valid : out std_logic; + source_ready : in std_logic; + source_sop : out std_logic; + source_eop : out std_logic; + source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0)); +end component auk_dspip_avalon_streaming_block_source_fir_91; + +component auk_dspip_avalon_streaming_block_sink_fir_91 is + generic ( + MAX_BLK_g : natural; + STALL_g : natural; + DATAWIDTH_g : natural; + -- this generic is specific for the FFT. + NUM_STAGES_g : natural); + port ( + clk : in std_logic; + reset : in std_logic; + in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); + in_sop : in std_logic; + in_eop : in std_logic; + in_inverse : in std_logic; + sink_valid : in std_logic; + sink_ready : out std_logic; + source_stall : in std_logic; + in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0); + processing : in std_logic; + in_error : in std_logic_vector(1 downto 0); + out_error : out std_logic_vector(1 downto 0); + out_valid : out std_logic; + out_sop : out std_logic; + out_eop : out std_logic; + out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0); + curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0); + -- these are specific to the FFT, no effort has been made to optimize! + curr_pwr_2 : out std_logic; + curr_inverse : out std_logic; + curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0)); +end component auk_dspip_avalon_streaming_block_sink_fir_91; + + + +end package auk_dspip_lib_pkg_hpfir; diff --git a/ld3/dds_vhdl/fir/auk_dspip_math_pkg_hpfir.vhd b/ld3/dds_vhdl/fir/auk_dspip_math_pkg_hpfir.vhd new file mode 100644 index 0000000..90a0e97 --- /dev/null +++ b/ld3/dds_vhdl/fir/auk_dspip_math_pkg_hpfir.vhd @@ -0,0 +1,370 @@ +-- (C) 2001-2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files from any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License Subscription +-- Agreement, Intel FPGA IP License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +-- (C) 2001-2009 Altera Corporation. All rights reserved. +-- Your use of Altera Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License Subscription +-- Agreement, Altera MegaCore Function License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +------------------------------------------------------------------------- +------------------------------------------------------------------------- +-- +-- Revision Control Information +-- +-- $Revision: #1 $ +-- $Date: 2009/07/29 $ +-- Check in by : $Author: max $ +-- Author : DSP_IP +-- +-- Project : +-- +-- Description : +-- +-- Common functions for DSP_IP cores. +-- +-- +-- ALTERA Confidential and Proprietary +-- Copyright 2006 (c) Altera Corporation +-- All rights reserved +-- +------------------------------------------------------------------------- +------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +use ieee.numeric_std.all; +PACKAGE auk_dspip_math_pkg_hpfir IS + + + ----------------------------------------------------------------------------- + -- NOTE that these log functions are not intended to synthesize directly + -- into hardware, rather they are used to generate constants for + -- synthesized hardware. + ----------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- LOG2_CEIL Function. + -- Effectively performs log2() followed by ceil() + -- e.g. CEIL_LOG2(255) returns 8 + -- CEIL_LOG2(256) returns 8 + -- CEIL_LOG2(257) returns 9 + --------------------------------------------------------------------------- + function log2_ceil(arg : in integer) return integer; + function log2_ceil_one(arg : in integer) return integer; -- log2_ceil(1)=0 + --------------------------------------------------------------------------- + -- LOG2_FLOOR Function. + -- Effectively performs log2() followed by floor() + -- e.g. CEIL_LOG2(255) returns 7 + -- CEIL_LOG2(256) returns 8 + -- CEIL_LOG2(257) returns 8 + --------------------------------------------------------------------------- + function log2_floor(arg : in integer) return integer; + + ----------------------------------------------------------------------------- + -- SIGN functions + ----------------------------------------------------------------------------- + -- returns the sign bit of a vector + function sign (arg : in signed) return std_logic; + + -- sign extends ARG to size SIZE. + function sign_extend (arg : signed; size : positive) return signed; + + -- sign extend one bit + function xt1 (arg : signed) return signed; + + --------------------------------------------------------------------------- + -- Arithmetic FUNCTIONs. + --------------------------------------------------------------------------- + -- Check integer for odd-ness + function is_odd(arg : integer) return boolean; + + ----------------------------------------------------------------------------- + -- Logical functions + ----------------------------------------------------------------------------- + -- Result of and'ing all of the bits of the vector. + function and_reduce(arg : std_logic_vector) return std_logic; + function and_reduce(arg : unsigned) return std_logic; + + -- Result of or'ing all of the bits of the vector. + function or_reduce(arg : std_logic_vector) return std_logic; + function or_reduce(arg : unsigned) return std_logic; + + -- returns index+1 of the highest asserted bit. + function highest_one(arg : unsigned) return natural; + + -- returns index+1 of the lowest asserted bit. + function lowest_one(arg : unsigned) return natural; + + -- returns the count of number of ones. + function count_ones(arg : unsigned) return natural; + + -- Bit reverse + function bit_reverse(arg : unsigned) return unsigned; + + -- Invert the argument bitwise + function invert(arg : unsigned) return unsigned; + + --Halve towards up + function halve_ceil(arg:natural) return natural; + + function div_ceil(a:natural;b:natural) return natural; + +END PACKAGE auk_dspip_math_pkg_hpfir; + +package body auk_dspip_math_pkg_hpfir is + --------------------------------------------------------------------------- + -- LOG2_CEIL Function. + --------------------------------------------------------------------------- + function log2_ceil(arg : in integer) return integer is + variable res : integer; + begin + res := 0; + for i in 0 to 30 loop + if (arg > (2**i)) then + res := i+1; + end if; + end loop; -- i + return res; + end log2_ceil; + --------------------------------------------------------------------------- + -- LOG2_CEIL_ONE Function. + --------------------------------------------------------------------------- + function log2_ceil_one(arg : in integer) return integer is + variable res : integer; + begin + res := 0; + for i in 0 to 30 loop + if (arg > (2**i)) then + res := i+1; + end if; + end loop; -- i + if res = 0 then + res := 1; + end if; + return res; + end log2_ceil_one; + + --------------------------------------------------------------------------- + -- LOG2_FLOOR Function. + ----------------------------------------------------------------------------- + function log2_floor(arg : in integer) return integer is + variable res : integer; + begin + res := 0; + for i in 0 to 30 loop + if (arg >= (2**i)) then + res := i; + end if; + end loop; -- i + return res; + end log2_floor; + + ----------------------------------------------------------------------------- + -- SIGN Function + ----------------------------------------------------------------------------- + function sign (arg : in signed) return std_logic is + variable res : std_logic; + begin + res := arg(arg'left); + return(res); + end sign; + + ----------------------------------------------------------------------------- + -- SIGN_EXTEND Function + ----------------------------------------------------------------------------- + function sign_extend (arg : signed; size : positive) return signed is + variable res : signed(size-1 downto 0); + begin + if arg'length > size then + assert arg'length < size report "WARNING, can't sign extend" severity warning; + end if; + for i in arg'length to size-1 loop + res(i) := arg(arg'left); + end loop; -- i + res(arg'length-1 downto 0) := arg; + return(res); + end sign_extend; + + ----------------------------------------------------------------------------- + -- XT1 Function + ----------------------------------------------------------------------------- + function xt1 (arg : signed) return signed is + variable res : signed(arg'length downto 0); + begin + res := arg(arg'left) & arg; + return(res); + end xt1; + + ----------------------------------------------------------------------------- + -- IS_ODD Function + ----------------------------------------------------------------------------- + function is_odd(arg : integer) return boolean is + begin + return ((arg mod 2) = 1); + end is_odd; + + + ----------------------------------------------------------------------------- + -- AND_REDUCE Function + ----------------------------------------------------------------------------- + function and_reduce(arg : std_logic_vector) return std_logic is + variable res : std_logic; + begin + res := '1'; + for i in arg'range loop + res := res and arg(i); + end loop; + return res; + end; + + function and_reduce(arg : unsigned) return std_logic is + variable res : std_logic; + begin + res := '1'; + for i in arg'range loop + res := res and arg(i); + end loop; + return res; + end; + + + ----------------------------------------------------------------------------- + -- OR_REDUCE Function + ----------------------------------------------------------------------------- + function or_reduce(arg : unsigned) return std_logic is + variable res : std_logic; + begin + res := '0'; + for i in arg'range loop + res := res or arg(i); + end loop; + return res; + end; + + function or_reduce(arg : std_logic_vector) return std_logic is + variable res : std_logic; + begin + res := '0'; + for i in arg'range loop + res := res or arg(i); + end loop; + return res; + end; + + --------------------------------------------------------------------------- + -- HIGHEST_ONE Function. + --------------------------------------------------------------------------- + -- Returns index+1 of the highest asserted bit, or 0 if no bit set. + -- Vector is evaluated from left to right, not high to low! + function highest_one(arg : unsigned) return natural is + begin + for i in arg'range loop + if arg(i) = '1' then + return i+1; + end if; + end loop; + return 0; + end; + + ----------------------------------------------------------------------------- + -- LOWEST_ONE Function + ----------------------------------------------------------------------------- + -- Returns index+1 of the lowest asserted bit, or 0 if no bit set. + -- Vector is evaluated from left to right, not high to low! + function lowest_one(arg : unsigned) return natural is + begin + for i in 0 to arg'length-1 loop + if (arg(i) = '1') then + return(i+1); + end if; + end loop; + return(0); + end; + + ----------------------------------------------------------------------------- + -- COUNT_ONES + --------------------------------------------------------------------------- + -- Returns the count of the number of ones. + function count_ones(arg : unsigned) return natural is + variable count : integer; + begin + count := 0; + for i in 0 to arg'length-1 loop + if (arg(i) = '1') then + count := count + 1; + end if; + end loop; + return count; + end; + + ----------------------------------------------------------------------------- + -- BIT_REVERSE function + ----------------------------------------------------------------------------- + function bit_reverse(arg : unsigned) return unsigned is + variable res : unsigned(arg'range); + begin + for i in arg'range loop + res(i) := arg(arg'high - i); + end loop; + return(res); + end; + + ----------------------------------------------------------------------------- + -- INVERT Function + ----------------------------------------------------------------------------- + function invert(arg : unsigned) + return unsigned -- (word'high downto 0) + is + variable res : unsigned(arg'high downto 0); + begin + + for i in arg'range loop + res(i) := not arg(i); + end loop; + return (res); + end invert; + + ----------------------------------------------------------------------------- + -- HALVE_CEIL Function + ----------------------------------------------------------------------------- + function halve_ceil(arg : natural) return natural is + variable res : natural; + begin + if is_odd(arg) then + res := (arg+1)/2; + else + res := arg/2; + end if; + return (res); + end halve_ceil; + +------------------------------------------------------------------------------- +-- DIV_CEIL function +------------------------------------------------------------------------------- + function div_ceil(a : natural; b : natural) return natural is + variable res : natural := a/b; + begin + if res*b /= a then + res := res +1; + end if; + return res; + end div_ceil; + +end package body auk_dspip_math_pkg_hpfir; diff --git a/ld3/dds_vhdl/fir/auk_dspip_roundsat_hpfir.vhd b/ld3/dds_vhdl/fir/auk_dspip_roundsat_hpfir.vhd new file mode 100644 index 0000000..8957587 --- /dev/null +++ b/ld3/dds_vhdl/fir/auk_dspip_roundsat_hpfir.vhd @@ -0,0 +1,187 @@ +-- (C) 2001-2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files from any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License Subscription +-- Agreement, Intel FPGA IP License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +------------------------------------------------------------------------- +------------------------------------------------------------------------- +-- +-- Revision Control Information +-- +-- $RCSfile: auk_dspip_roundsat_hpfir.vhd,v $ +-- +-- $Revision: #1 $ +-- $Date: 2010/08/19 $ +-- Check in by : $Author: max $ +-- +-- Description : +-- Implement output options for HP-FIR +-- +-- ALTERA Confidential and Proprietary +-- Copyright 2006 (c) Altera Corporation +-- All rights reserved +-- +------------------------------------------------------------------------- +------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity auk_dspip_roundsat_hpfir is + generic ( + IN_WIDTH_g : natural := 8; -- i/p data width + REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed + REM_LSB_TYPE_g : string := "trunc"; -- trunc/round + REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed + REM_MSB_TYPE_g : string := "trunc" -- trunc/sat + ); + port ( + clk : in std_logic; + reset_n : in std_logic; + enable : in std_logic; + datain : in std_logic_vector(IN_WIDTH_g-1 downto 0); + valid : out std_logic; + dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0) + ); +end entity auk_dspip_roundsat_hpfir; + +architecture beh of auk_dspip_roundsat_hpfir is + + signal data_lsb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-1 downto 0); + signal valid_lsb : std_logic; + + signal data_msb : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); + + constant zero_vec : std_logic_vector := std_logic_vector(to_signed(0, REM_LSB_BIT_g)); + +begin -- architecture beh + + ----------------------------------------------------------------------------- + -- lsb : trunc/round-up (symmetric) + ----------------------------------------------------------------------------- + remove_lsb: if REM_LSB_BIT_g > 0 generate + begin + trunc_lsb: if REM_LSB_TYPE_g = "trunc" generate + begin + data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); + valid_lsb <= enable; + end generate trunc_lsb; + rndup_lsb: if REM_LSB_TYPE_g = "round" generate + round_up_sym_p : process (clk, reset_n) + variable OR_accu : std_logic := '0'; + begin + if reset_n = '0' then + data_lsb <= (others => '0'); + valid_lsb <= '0'; + elsif rising_edge(clk) then + if enable = '1' then + OR_accu := '0'; + for i in 0 to REM_LSB_BIT_g-2 loop + OR_accu := OR_accu or datain(i); + end loop; + -- negative value + if (datain(IN_WIDTH_g-1) = '1') then + -- larger than -x.5 : rounded to -x + if (datain(REM_LSB_BIT_g-1)='1' and OR_accu='1') then + data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1); + -- less than or equal -x.5 : rounded to -x + 1 + else + data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); + end if; + -- positive value + else + -- maximum positive value + if datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g-1) = std_logic_vector(to_signed(2**(IN_WIDTH_g-REM_LSB_BIT_g)-1, IN_WIDTH_g-REM_LSB_BIT_g+1)) then + data_lsb <= std_logic_vector(to_signed( 2**(IN_WIDTH_g-REM_LSB_BIT_g-1)-1, IN_WIDTH_g-REM_LSB_BIT_g)); + -- larger than or equal x.5 : rounded to x + 1 + elsif datain(REM_LSB_BIT_g-1) = '1' then + data_lsb <= std_logic_vector(signed(datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g))+1); + -- less than x.5 : rounded to x + else + data_lsb <= datain(IN_WIDTH_g-1 downto REM_LSB_BIT_g); + end if; + end if; + end if; + valid_lsb <= enable; + end if; + end process round_up_sym_p; + end generate rndup_lsb; + end generate remove_lsb; + + ----------------------------------------------------------------------------- + -- keep lsb + ----------------------------------------------------------------------------- + keep_lsb: if REM_LSB_BIT_g = 0 generate + begin + data_lsb <= datain; + valid_lsb <= enable; + end generate keep_lsb; + + ----------------------------------------------------------------------------- + -- msb : trunc/saturation + ----------------------------------------------------------------------------- + remove_msb: if REM_MSB_BIT_g > 0 generate + signal min_val, max_val : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); + begin + trunc_msb: if REM_MSB_TYPE_g = "trunc" generate + begin + data_msb <= data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); + dataout <= data_msb; + valid <= valid_lsb; + end generate trunc_msb; + + sat_msb: if REM_MSB_TYPE_g = "sat" generate + max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '0'; + max_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '1'); + min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1) <= '1'; + min_val(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-2 downto 0) <= (others => '0'); + data_msb <= std_logic_vector(max_val) when signed(data_lsb) > signed(max_val) else + std_logic_vector(min_val) when signed(data_lsb) < signed(min_val) else + data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); + msb_p : process (clk, reset_n) + begin + if reset_n = '0' then + dataout <= (others => '0'); + valid <= '0'; + elsif rising_edge(clk) then + if valid_lsb = '1' then + dataout <= data_msb; + end if; + valid <= valid_lsb; + end if; + end process msb_p; + end generate sat_msb; + end generate remove_msb; + + ----------------------------------------------------------------------------- + -- keep msb + ----------------------------------------------------------------------------- + keep_msb: if REM_MSB_BIT_g = 0 generate + begin + data_msb <= data_lsb; + dataout <= data_msb; + valid <= valid_lsb; + end generate keep_msb; + + ----------------------------------------------------------------------------- + -- error checking: + -- Have we got a valid round mode? + -- Is the input greater than the output? + ----------------------------------------------------------------------------- + assert (REM_LSB_TYPE_g = "trunc" or + REM_LSB_TYPE_g = "round" or + REM_MSB_TYPE_g = "trunc" or + REM_MSB_TYPE_g = "sat" + ) report "Please check your round type and its spelling. Currently, we only support trunc, and round for LSB, trunc and sat for MSB" severity error; + + +end architecture beh; diff --git a/ld3/dds_vhdl/fir/dspba_library.vhd b/ld3/dds_vhdl/fir/dspba_library.vhd new file mode 100644 index 0000000..d34ad28 --- /dev/null +++ b/ld3/dds_vhdl/fir/dspba_library.vhd @@ -0,0 +1,377 @@ +-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files any of the foregoing device programming or simulation files), and +-- any associated documentation or information are expressly subject to the +-- terms and conditions of the Intel FPGA Software License Agreement, +-- Intel MegaCore Function License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for the sole +-- purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +library IEEE; +use IEEE.std_logic_1164.all; +use work.dspba_library_package.all; + +entity dspba_delay is + generic ( + width : natural := 8; + depth : natural := 1; + reset_high : std_logic := '1'; + reset_kind : string := "ASYNC" + ); + port ( + clk : in std_logic; + aclr : in std_logic; + ena : in std_logic := '1'; + xin : in std_logic_vector(width-1 downto 0); + xout : out std_logic_vector(width-1 downto 0) + ); +end dspba_delay; + +architecture delay of dspba_delay is + type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0); + signal delay_signals : delay_array; +begin + delay_signals(depth) <= xin; + + delay_block: if 0 < depth generate + begin + delay_loop: for i in depth-1 downto 0 generate + begin + async_reset: if reset_kind = "ASYNC" generate + process(clk, aclr) + begin + if aclr=reset_high then + delay_signals(i) <= (others => '0'); + elsif clk'event and clk='1' then + if ena='1' then + delay_signals(i) <= delay_signals(i + 1); + end if; + end if; + end process; + end generate; + + sync_reset: if reset_kind = "SYNC" generate + process(clk) + begin + if clk'event and clk='1' then + if aclr=reset_high then + delay_signals(i) <= (others => '0'); + elsif ena='1' then + delay_signals(i) <= delay_signals(i + 1); + end if; + end if; + end process; + end generate; + + no_reset: if reset_kind = "NONE" generate + process(clk) + begin + if clk'event and clk='1' then + if ena='1' then + delay_signals(i) <= delay_signals(i + 1); + end if; + end if; + end process; + end generate; + end generate; + end generate; + + xout <= delay_signals(0); +end delay; + +-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; +use work.dspba_library_package.all; + +entity dspba_sync_reg is + generic ( + width1 : natural := 8; + init_value : std_logic_vector; + width2 : natural := 8; + depth : natural := 2; + pulse_multiplier : natural := 1; + counter_width : natural := 8; + reset1_high : std_logic := '1'; + reset2_high : std_logic := '1'; + reset_kind : string := "ASYNC" + ); + port ( + clk1 : in std_logic; + aclr1 : in std_logic; + ena : in std_logic_vector(0 downto 0); + xin : in std_logic_vector(width1-1 downto 0); + xout : out std_logic_vector(width1-1 downto 0); + clk2 : in std_logic; + aclr2 : in std_logic; + sxout : out std_logic_vector(width2-1 downto 0) + ); +end entity; + +architecture sync_reg of dspba_sync_reg is + type bit_array is array (depth-1 downto 0) of std_logic; + + signal iclk_enable : std_logic; + signal iclk_data : std_logic_vector(width1-1 downto 0); + signal oclk_data : std_logic_vector(width2-1 downto 0); + + -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops + -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis + signal sync_regs : bit_array; + attribute altera_attribute : string; + attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; + + signal oclk_enable : std_logic; + + constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value; + + signal counter : UNSIGNED(counter_width-1 downto 0); + signal ena_internal : std_logic; +begin + oclk_enable <= sync_regs(depth-1); + + no_multiplication: if pulse_multiplier=1 generate + ena_internal <= ena(0); + end generate; + + async_reset: if reset_kind="ASYNC" generate + + multiply_ena: if pulse_multiplier>1 generate + ena_internal <= '1' when counter>0 else ena(0); + process (clk1, aclr1) + begin + if aclr1=reset1_high then + counter <= (others => '0'); + elsif clk1'event and clk1='1' then + if counter>0 then + if counter=pulse_multiplier-1 then + counter <= (others => '0'); + else + counter <= counter + TO_UNSIGNED(1, counter_width); + end if; + else + if ena(0)='1' then + counter <= TO_UNSIGNED(1, counter_width); + end if; + end if; + end if; + end process; + end generate; + + process (clk1, aclr1) + begin + if aclr1=reset1_high then + iclk_enable <= '0'; + iclk_data <= init_value_internal; + elsif clk1'event and clk1='1' then + iclk_enable <= ena_internal; + if ena(0)='1' then + iclk_data <= xin; + end if; + end if; + end process; + + sync_reg_loop: for i in 0 to depth-1 generate + process (clk2, aclr2) + begin + if aclr2=reset2_high then + sync_regs(i) <= '0'; + elsif clk2'event and clk2='1' then + if i>0 then + sync_regs(i) <= sync_regs(i-1); + else + sync_regs(i) <= iclk_enable; + end if; + end if; + end process; + end generate; + + process (clk2, aclr2) + begin + if aclr2=reset2_high then + oclk_data <= init_value_internal(width2-1 downto 0); + elsif clk2'event and clk2='1' then + if oclk_enable='1' then + oclk_data <= iclk_data(width2-1 downto 0); + end if; + end if; + end process; + end generate; + + sync_reset: if reset_kind="SYNC" generate + + multiply_ena: if pulse_multiplier>1 generate + ena_internal <= '1' when counter>0 else ena(0); + process (clk1) + begin + if clk1'event and clk1='1' then + if aclr1=reset1_high then + counter <= (others => '0'); + else + if counter>0 then + if counter=pulse_multiplier-1 then + counter <= (others => '0'); + else + counter <= counter + TO_UNSIGNED(1, counter_width); + end if; + else + if ena(0)='1' then + counter <= TO_UNSIGNED(1, counter_width); + end if; + end if; + end if; + end if; + end process; + end generate; + + process (clk1) + begin + if clk1'event and clk1='1' then + if aclr1=reset1_high then + iclk_enable <= '0'; + iclk_data <= init_value_internal; + else + iclk_enable <= ena_internal; + if ena(0)='1' then + iclk_data <= xin; + end if; + end if; + end if; + end process; + + sync_reg_loop: for i in 0 to depth-1 generate + process (clk2) + begin + if clk2'event and clk2='1' then + if aclr2=reset2_high then + sync_regs(i) <= '0'; + else + if i>0 then + sync_regs(i) <= sync_regs(i-1); + else + sync_regs(i) <= iclk_enable; + end if; + end if; + end if; + end process; + end generate; + + process (clk2) + begin + if clk2'event and clk2='1' then + if aclr2=reset2_high then + oclk_data <= init_value_internal(width2-1 downto 0); + elsif oclk_enable='1' then + oclk_data <= iclk_data(width2-1 downto 0); + end if; + end if; + end process; + end generate; + + none_reset: if reset_kind="NONE" generate + + multiply_ena: if pulse_multiplier>1 generate + ena_internal <= '1' when counter>0 else ena(0); + process (clk1, aclr1) + begin + if clk1'event and clk1='1' then + if counter>0 then + if counter=pulse_multiplier-1 then + counter <= (others => '0'); + else + counter <= counter + TO_UNSIGNED(1, counter_width); + end if; + else + if ena(0)='1' then + counter <= TO_UNSIGNED(1, counter_width); + end if; + end if; + end if; + end process; + end generate; + + process (clk1) + begin + if clk1'event and clk1='1' then + iclk_enable <= ena_internal; + if ena(0)='1' then + iclk_data <= xin; + end if; + end if; + end process; + + sync_reg_loop: for i in 0 to depth-1 generate + process (clk2) + begin + if clk2'event and clk2='1' then + if i>0 then + sync_regs(i) <= sync_regs(i-1); + else + sync_regs(i) <= iclk_enable; + end if; + end if; + end process; + end generate; + + process (clk2) + begin + if clk2'event and clk2='1' then + if oclk_enable='1' then + oclk_data <= iclk_data(width2-1 downto 0); + end if; + end if; + end process; + end generate; + + xout <= iclk_data; + sxout <= oclk_data; + +end sync_reg; + +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dspba_pipe is + generic( + num_bits : positive := 8; + num_stages : natural := 0; + init_value : std_logic := 'X' + ); + port( + clk: in std_logic; + d : in std_logic_vector(num_bits-1 downto 0); + q : out std_logic_vector(num_bits-1 downto 0) + ); +end entity dspba_pipe; + +architecture rtl of dspba_pipe is + attribute altera_attribute : string; + attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; + + type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0); + signal stage_array : stage_array_type := (others => (others => init_value)); +begin + stage_array(0) <= d; + + g_pipe : for i in 1 to num_stages generate + p_stage : process (clk) is + begin + if rising_edge(clk) then + stage_array(i) <= stage_array(i-1); + end if; + end process p_stage; + end generate g_pipe; + + q <= stage_array(num_stages); + +end rtl; + diff --git a/ld3/dds_vhdl/fir/dspba_library_package.vhd b/ld3/dds_vhdl/fir/dspba_library_package.vhd new file mode 100644 index 0000000..d609280 --- /dev/null +++ b/ld3/dds_vhdl/fir/dspba_library_package.vhd @@ -0,0 +1,72 @@ +-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files any of the foregoing device programming or simulation files), and +-- any associated documentation or information are expressly subject to the +-- terms and conditions of the Intel FPGA Software License Agreement, +-- Intel MegaCore Function License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for the sole +-- purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +library IEEE; +use IEEE.std_logic_1164.all; + +package dspba_library_package is + + component dspba_delay is + generic ( + width : natural := 8; + depth : natural := 1; + reset_high : std_logic := '1'; + reset_kind : string := "ASYNC" + ); + port ( + clk : in std_logic; + aclr : in std_logic; + ena : in std_logic := '1'; + xin : in std_logic_vector(width-1 downto 0); + xout : out std_logic_vector(width-1 downto 0) + ); + end component; + + component dspba_sync_reg is + generic ( + width1 : natural := 8; + width2 : natural := 8; + depth : natural := 2; + init_value : std_logic_vector; + pulse_multiplier : natural := 1; + counter_width : natural := 8; + reset1_high : std_logic := '1'; + reset2_high : std_logic := '1'; + reset_kind : string := "ASYNC" + ); + port ( + clk1 : in std_logic; + aclr1 : in std_logic; + ena : in std_logic_vector(0 downto 0); + xin : in std_logic_vector(width1-1 downto 0); + xout : out std_logic_vector(width1-1 downto 0); + clk2 : in std_logic; + aclr2 : in std_logic; + sxout : out std_logic_vector(width2-1 downto 0) + ); + end component; + + component dspba_pipe is + generic( + num_bits : positive; + num_stages : natural; + init_value : std_logic := 'X' + ); + port( + clk: in std_logic; + d : in std_logic_vector(num_bits-1 downto 0); + q : out std_logic_vector(num_bits-1 downto 0) + ); + end component dspba_pipe; + +end dspba_library_package; diff --git a/ld3/dds_vhdl/fir/fir_0002.vhd b/ld3/dds_vhdl/fir/fir_0002.vhd new file mode 100644 index 0000000..6e9d868 --- /dev/null +++ b/ld3/dds_vhdl/fir/fir_0002.vhd @@ -0,0 +1,82 @@ +-- (C) 2001-2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files from any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License Subscription +-- Agreement, Intel FPGA IP License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for the +-- sole purpose of programming logic devices manufactured by Intel and sold by +-- Intel or its authorized distributors. Please refer to the applicable +-- agreement for further details. + + +library IEEE; +use IEEE.std_logic_1164.all; +use work.auk_dspip_lib_pkg_hpfir.all; +use work.auk_dspip_math_pkg_hpfir.all; + +entity fir_0002 is + port ( + clk : in STD_LOGIC; + reset_n : in STD_LOGIC; + ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0); + ast_sink_valid : in STD_LOGIC; + ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); + ast_source_data : out STD_LOGIC_VECTOR(37 * 1*1 - 1 downto 0); + ast_source_valid : out STD_LOGIC; + ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) + ); +end fir_0002; + + +architecture syn of fir_0002 is + component fir_0002_ast + port ( + clk : in STD_LOGIC; + reset_n : in STD_LOGIC; + ast_sink_data : in STD_LOGIC_VECTOR((0 + 1*16) * 1 + 0 - 1 downto 0); + ast_sink_valid : in STD_LOGIC; + ast_sink_ready : out STD_LOGIC; + ast_sink_sop : in STD_LOGIC; + ast_sink_eop : in STD_LOGIC; + ast_sink_error : in STD_LOGIC_VECTOR(1 downto 0); + ast_source_data : out STD_LOGIC_VECTOR(1*37 * 1 - 1 downto 0); + ast_source_ready : in STD_LOGIC; + ast_source_valid : out STD_LOGIC; + ast_source_sop : out STD_LOGIC; + ast_source_eop : out STD_LOGIC; + ast_source_channel : out STD_LOGIC_VECTOR(log2_ceil_one(1) - 1 downto 0); + ast_source_error : out STD_LOGIC_VECTOR(1 downto 0) + ); +end component; + + signal coeff_in_read_sig : std_logic; + +begin + + coeff_in_read_sig <= '1'; + + + + fir_0002_ast_inst : fir_0002_ast + port map ( + clk => clk, + reset_n => reset_n, + ast_sink_data => ast_sink_data, + ast_source_data => ast_source_data, + ast_sink_valid => ast_sink_valid, + ast_sink_ready => open, + ast_source_ready => '1', + ast_source_valid => ast_source_valid, + ast_sink_sop => '0', + ast_sink_eop => '0', + ast_sink_error => ast_sink_error, + ast_source_sop => open, + ast_source_eop => open, + ast_source_channel => open, + ast_source_error => ast_source_error + ); +end syn; + + diff --git a/ld3/dds_vhdl/fir/fir_0002_ast.vhd b/ld3/dds_vhdl/fir/fir_0002_ast.vhd new file mode 100644 index 0000000..5ea41c1 --- /dev/null +++ b/ld3/dds_vhdl/fir/fir_0002_ast.vhd @@ -0,0 +1,273 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.auk_dspip_lib_pkg_hpfir.all; +use work.auk_dspip_math_pkg_hpfir.all; + +entity fir_0002_ast is + generic ( + INWIDTH : integer := 16; + OUT_WIDTH_UNTRIMMED : integer := 37; + BANKINWIDTH : integer := 0; + REM_LSB_BIT_g : integer := 0; + REM_LSB_TYPE_g : string := "trunc"; + REM_MSB_BIT_g : integer := 0; + REM_MSB_TYPE_g : string := "trunc"; + PHYSCHANIN : integer := 1; + PHYSCHANOUT : integer := 1; + CHANSPERPHYIN : natural := 1; + CHANSPERPHYOUT : natural := 1; + OUTPUTFIFODEPTH : integer := 8; + USE_PACKETS : integer := 0; + MODE_WIDTH : integer := 0; + ENABLE_BACKPRESSURE : boolean := false; + LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1); + NUMCHANS : integer := 1; + DEVICE_FAMILY : string := "Cyclone V"; + COMPLEX_CONST : integer := 1 + ); + port( + clk : in std_logic; + reset_n : in std_logic; + ast_sink_ready : out std_logic; + ast_source_data : out std_logic_vector(COMPLEX_CONST*(OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0); + ast_sink_data : in std_logic_vector( COMPLEX_CONST*(INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); + ast_sink_valid : in std_logic; + ast_source_valid : out std_logic; + ast_source_ready : in std_logic; + ast_source_eop : out std_logic; + ast_source_sop : out std_logic; + ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0); + ast_sink_eop : in std_logic; + ast_sink_sop : in std_logic; + ast_sink_error : in std_logic_vector (1 downto 0); + ast_source_error : out std_logic_vector (1 downto 0) + ); +attribute altera_attribute : string; +attribute altera_attribute of fir_0002_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036"; +end fir_0002_ast; + +-- Warnings Suppression On +-- altera message_off 10036 + +architecture struct of fir_0002_ast is + + constant OUTWIDTH : integer := OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g; + + signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0); + + signal core_channel_out : std_logic_vector(2 -1 downto 0); + signal at_source_channel : std_logic_vector(2 -1 downto 0); + signal sink_packet_error : std_logic_vector(1 downto 0); + signal data_in : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); + signal data_valid : std_logic_vector(0 downto 0); + + signal data_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT -1 downto 0); + signal reset_fir : std_logic; + signal sink_ready_ctrl : std_logic; + signal source_packet_error : std_logic_vector(1 downto 0); + signal source_stall : std_logic; + signal source_valid_ctrl : std_logic; + signal stall : std_logic; + signal valid : std_logic; + signal core_valid : std_logic; + signal enable_in : std_logic_vector(0 downto 0); + + signal outp_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT - 1 downto 0); + signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0); + + signal core_out : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0); + signal core_out_valid : std_logic_vector(0 downto 0); + signal core_out_channel : std_logic_vector(7 downto 0); + + signal core_out_channel_0 : std_logic_vector(7 downto 0); + + +begin + sink : auk_dspip_avalon_streaming_sink_hpfir + generic map ( + WIDTH_g => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH, + DATA_WIDTH => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH, + DATA_PORT_COUNT => 1, + PACKET_SIZE_g => CHANSPERPHYIN) + port map ( + clk => clk, + reset_n => reset_n, + data => data_in, + data_valid => data_valid, + sink_ready_ctrl => sink_ready_ctrl, + packet_error => sink_packet_error, + at_sink_ready => ast_sink_ready, + at_sink_valid => ast_sink_valid, + at_sink_data => ast_sink_data, + at_sink_sop => ast_sink_sop, + at_sink_eop => ast_sink_eop, + at_sink_error => ast_sink_error); + + source : auk_dspip_avalon_streaming_source_hpfir + generic map ( + WIDTH_g => COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT, + DATA_WIDTH => COMPLEX_CONST*OUTWIDTH, + DATA_PORT_COUNT => PHYSCHANOUT, + FIFO_DEPTH_g => OUTPUTFIFODEPTH, + USE_PACKETS => USE_PACKETS, + HAVE_COUNTER_g => false, + PACKET_SIZE_g => CHANSPERPHYOUT, + COUNTER_LIMIT_g => CHANSPERPHYOUT, + ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE) + port map ( + clk => clk, + reset_n => reset_n, + data_in => data_out, + data_count => channel_out, + source_valid_ctrl => source_valid_ctrl, + source_stall => source_stall, + packet_error => source_packet_error, + at_source_ready => ast_source_ready, + at_source_valid => ast_source_valid, + at_source_data => ast_source_data, + at_source_channel => ast_source_channel, + at_source_sop => ast_source_sop, + at_source_eop => ast_source_eop, + at_source_error => ast_source_error); + + + intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir + port map ( + clk => clk, + reset_n => reset_n, + sink_packet_error => sink_packet_error, + source_stall => source_stall, + valid => valid, + reset_design => reset_fir, + sink_ready_ctrl => sink_ready_ctrl, + source_packet_error => source_packet_error, + source_valid_ctrl => source_valid_ctrl, + stall => stall); + + + + multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate + data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)); + end generate multi_data_out; + + channel_pipe_lsb: if REM_LSB_TYPE_g = "round" and REM_LSB_BIT_g > 0 generate + begin + out_lsb_p : process (clk, reset_n) + begin + if reset_n = '0' then + core_out_channel_0 <= (others => '0'); + elsif rising_edge(clk) then + core_out_channel_0 <= core_out_channel; + end if; + end process out_lsb_p; + end generate channel_pipe_lsb; + + channel_wire_lsb: if REM_LSB_TYPE_g = "trunc" or REM_LSB_BIT_g = 0 generate + begin + core_out_channel_0 <= core_out_channel; + end generate channel_wire_lsb; + + channel_pipe_msb: if REM_MSB_TYPE_g = "sat" and REM_MSB_BIT_g > 0 generate + begin + out_p : process (clk, reset_n) + begin + if reset_n = '0' then + channel_out <= (others => '0'); + elsif rising_edge(clk) then + channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0); + end if; + end process out_p; + end generate channel_pipe_msb; + + channel_wire_msb: if REM_MSB_TYPE_g = "trunc" or REM_MSB_BIT_g = 0 generate + begin + channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0); + end generate channel_wire_msb; + + +real_passthrough : if COMPLEX_CONST = 1 generate + + component fir_0002_rtl_core is + port ( + xIn_v : in std_logic_vector(0 downto 0); + xIn_c : in std_logic_vector(7 downto 0); + xIn_0 : in std_logic_vector(16 - 1 downto 0); + xOut_v : out std_logic_vector(0 downto 0); + xOut_c : out std_logic_vector(7 downto 0); + xOut_0 : out std_logic_vector(37- 1 downto 0); + clk : in std_logic; + areset : in std_logic + ); +end component fir_0002_rtl_core; + + + --Complex data re-ordering + signal core_channel_out_core : std_logic_vector(2 -1 downto 0); + signal data_in_core : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0); + signal data_valid_core : std_logic_vector(0 downto 0); + signal core_out_core : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0); + signal core_out_valid_core : std_logic_vector(0 downto 0); + signal core_out_channel_core : std_logic_vector(7 downto 0); + + + + begin + hpfircore_core: fir_0002_rtl_core + port map ( + xIn_v => data_valid_core, + xIn_c => "00000000", + xIn_0 => data_in_core((0 + 16) * 0 + 16 - 1 downto (0 + 16) * 0), + xOut_v => core_out_valid_core, + xOut_c => core_out_channel_core, + xOut_0 => core_out_core(37* 0 + 37- 1 downto 37* 0), + clk => clk, + areset => reset_fir + ); + + + + + core_channel_out <= core_channel_out_core; + data_in_core <= data_in; + data_valid_core <= data_valid; + core_out <= core_out_core; + core_out_valid(0) <= core_out_valid_core(0); + core_out_channel <= core_out_channel_core; + + + + gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate + begin + outp_blk : auk_dspip_roundsat_hpfir + generic map ( + IN_WIDTH_g => OUT_WIDTH_UNTRIMMED , + REM_LSB_BIT_g => REM_LSB_BIT_g , + REM_LSB_TYPE_g => REM_LSB_TYPE_g , + REM_MSB_BIT_g => REM_MSB_BIT_g , + REM_MSB_TYPE_g => REM_MSB_TYPE_g + ) + port map ( + clk => clk, + reset_n => reset_n, + enable => core_out_valid(0), + datain => core_out(((i*OUT_WIDTH_UNTRIMMED)+OUT_WIDTH_UNTRIMMED-1) downto (i*OUT_WIDTH_UNTRIMMED)), + valid => outp_blk_valid(i), + dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH)) + ); + end generate gen_outp_blk; + end generate real_passthrough; + + + + valid <= outp_blk_valid(0); + + enable_in(0) <= not stall; + +end struct; + + + + diff --git a/ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd b/ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd new file mode 100644 index 0000000..ef1793c --- /dev/null +++ b/ld3/dds_vhdl/fir/fir_0002_rtl_core.vhd @@ -0,0 +1,1033 @@ +-- ------------------------------------------------------------------------- +-- High Level Design Compiler for Intel(R) FPGAs Version 19.1 (Release Build #670) +-- Quartus Prime development tool and MATLAB/Simulink Interface +-- +-- Legal Notice: Copyright 2019 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions and other +-- software and tools, and its AMPP partner logic functions, and any output +-- files any of the foregoing (including device programming or simulation +-- files), and any associated documentation or information are expressly +-- subject to the terms and conditions of the Intel FPGA Software License +-- Agreement, Intel MegaCore Function License Agreement, or other applicable +-- license agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by Intel +-- and sold by Intel or its authorized distributors. Please refer to the +-- applicable agreement for further details. +-- --------------------------------------------------------------------------- + +-- VHDL created from fir_0002_rtl_core +-- VHDL created on Tue Jun 09 18:16:08 2020 + + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; +use IEEE.MATH_REAL.all; +use std.TextIO.all; +use work.dspba_library_package.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; +LIBRARY altera_lnsim; +USE altera_lnsim.altera_lnsim_components.altera_syncram; +LIBRARY lpm; +USE lpm.lpm_components.all; + +entity fir_0002_rtl_core is + port ( + xIn_v : in std_logic_vector(0 downto 0); -- sfix1 + xIn_c : in std_logic_vector(7 downto 0); -- sfix8 + xIn_0 : in std_logic_vector(15 downto 0); -- sfix16 + xOut_v : out std_logic_vector(0 downto 0); -- ufix1 + xOut_c : out std_logic_vector(7 downto 0); -- ufix8 + xOut_0 : out std_logic_vector(36 downto 0); -- sfix37 + clk : in std_logic; + areset : in std_logic + ); +end fir_0002_rtl_core; + +architecture normal of fir_0002_rtl_core is + + attribute altera_attribute : string; + attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007"; + + signal GND_q : STD_LOGIC_VECTOR (0 downto 0); + signal VCC_q : STD_LOGIC_VECTOR (0 downto 0); + signal d_u0_m0_wo0_compute_q_11_q : STD_LOGIC_VECTOR (0 downto 0); + signal d_u0_m0_wo0_compute_q_12_q : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_cma0_reset : std_logic; + type u0_m0_wo0_cma0_a0type is array(NATURAL range <>) of SIGNED(15 downto 0); + signal u0_m0_wo0_cma0_a0 : u0_m0_wo0_cma0_a0type(0 to 31); + attribute preserve : boolean; + attribute preserve of u0_m0_wo0_cma0_a0 : signal is true; + type u0_m0_wo0_cma0_c0type is array(NATURAL range <>) of UNSIGNED(2 downto 0); + signal u0_m0_wo0_cma0_c0 : u0_m0_wo0_cma0_c0type(0 to 31); + attribute preserve of u0_m0_wo0_cma0_c0 : signal is true; + type u0_m0_wo0_cma0_rtype is array(NATURAL range <>) of SIGNED(14 downto 0); + signal u0_m0_wo0_cma0_r : u0_m0_wo0_cma0_rtype(0 to 31); + type u0_m0_wo0_cma0_ptype is array(NATURAL range <>) of SIGNED(30 downto 0); + signal u0_m0_wo0_cma0_p : u0_m0_wo0_cma0_ptype(0 to 31); + type u0_m0_wo0_cma0_utype is array(NATURAL range <>) of SIGNED(35 downto 0); + signal u0_m0_wo0_cma0_u : u0_m0_wo0_cma0_utype(0 to 31); + signal u0_m0_wo0_cma0_w : u0_m0_wo0_cma0_utype(0 to 31); + signal u0_m0_wo0_cma0_x : u0_m0_wo0_cma0_utype(0 to 31); + signal u0_m0_wo0_cma0_y : u0_m0_wo0_cma0_utype(0 to 31); + signal u0_m0_wo0_cma0_k0 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-1299,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k1 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-1264,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k2 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-1050,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k3 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-427,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k4 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(712,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k5 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(2350,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k6 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(4113,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k7 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(5360,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k8 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(5377,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k9 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(3686,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k10 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(267,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k11 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-4309,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k12 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-8868,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k13 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-12055,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k14 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-12679,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k15 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-10168,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k16 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-4790,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k17 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(2297,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k18 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(9348,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k19 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(14495,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k20 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(16382,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k21 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(14495,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k22 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(9348,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k23 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(2297,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k24 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-4790,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k25 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-10168,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k26 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-12679,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k27 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-12055,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k28 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-8868,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k29 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(-4309,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k30 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(267,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_k31 : u0_m0_wo0_cma0_rtype(0 to 7) := ( + 0 => TO_SIGNED(3686,15), + others => (others => '0')); + signal u0_m0_wo0_cma0_s : u0_m0_wo0_cma0_utype(0 to 31); + signal u0_m0_wo0_cma0_qq : STD_LOGIC_VECTOR (35 downto 0); + signal u0_m0_wo0_cma0_q : STD_LOGIC_VECTOR (35 downto 0); + signal u0_m0_wo0_cma0_ena0 : std_logic; + signal u0_m0_wo0_cma0_ena1 : std_logic; + signal u0_m0_wo0_cma1_reset : std_logic; + signal u0_m0_wo0_cma1_a0 : u0_m0_wo0_cma0_a0type(0 to 9); + attribute preserve of u0_m0_wo0_cma1_a0 : signal is true; + signal u0_m0_wo0_cma1_c0 : u0_m0_wo0_cma0_c0type(0 to 9); + attribute preserve of u0_m0_wo0_cma1_c0 : signal is true; + type u0_m0_wo0_cma1_rtype is array(NATURAL range <>) of SIGNED(13 downto 0); + signal u0_m0_wo0_cma1_r : u0_m0_wo0_cma1_rtype(0 to 9); + type u0_m0_wo0_cma1_ptype is array(NATURAL range <>) of SIGNED(29 downto 0); + signal u0_m0_wo0_cma1_p : u0_m0_wo0_cma1_ptype(0 to 9); + type u0_m0_wo0_cma1_utype is array(NATURAL range <>) of SIGNED(33 downto 0); + signal u0_m0_wo0_cma1_u : u0_m0_wo0_cma1_utype(0 to 9); + signal u0_m0_wo0_cma1_w : u0_m0_wo0_cma1_utype(0 to 9); + signal u0_m0_wo0_cma1_x : u0_m0_wo0_cma1_utype(0 to 9); + signal u0_m0_wo0_cma1_y : u0_m0_wo0_cma1_utype(0 to 9); + signal u0_m0_wo0_cma1_k0 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(5377,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k1 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(5360,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k2 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(4113,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k3 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(2350,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k4 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(712,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k5 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(-427,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k6 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(-1050,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k7 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(-1264,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k8 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + 0 => TO_SIGNED(-1299,14), + others => (others => '0')); + signal u0_m0_wo0_cma1_k9 : u0_m0_wo0_cma1_rtype(0 to 7) := ( + others => (others => '0')); + signal u0_m0_wo0_cma1_s : u0_m0_wo0_cma1_utype(0 to 9); + signal u0_m0_wo0_cma1_qq : STD_LOGIC_VECTOR (33 downto 0); + signal u0_m0_wo0_cma1_q : STD_LOGIC_VECTOR (33 downto 0); + signal u0_m0_wo0_cma1_ena0 : std_logic; + signal u0_m0_wo0_cma1_ena1 : std_logic; + signal u0_m0_wo0_mtree_add0_0_a : STD_LOGIC_VECTOR (36 downto 0); + signal u0_m0_wo0_mtree_add0_0_b : STD_LOGIC_VECTOR (36 downto 0); + signal u0_m0_wo0_mtree_add0_0_o : STD_LOGIC_VECTOR (36 downto 0); + signal u0_m0_wo0_mtree_add0_0_q : STD_LOGIC_VECTOR (36 downto 0); + signal u0_m0_wo0_oseq_gated_reg_q : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_mem_reset0 : std_logic; + signal u0_m0_wo0_wi0_r0_delayr32_mem_ia : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_mem_aa : STD_LOGIC_VECTOR (4 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_mem_ab : STD_LOGIC_VECTOR (4 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_mem_iq : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_mem_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_rdcnt_q : STD_LOGIC_VECTOR (4 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_rdcnt_i : UNSIGNED (4 downto 0); + attribute preserve of u0_m0_wo0_wi0_r0_delayr32_rdcnt_i : signal is true; + signal u0_m0_wo0_wi0_r0_delayr32_rdcnt_eq : std_logic; + attribute preserve of u0_m0_wo0_wi0_r0_delayr32_rdcnt_eq : signal is true; + signal u0_m0_wo0_wi0_r0_delayr32_wraddr_q : STD_LOGIC_VECTOR (4 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_mem_last_q : STD_LOGIC_VECTOR (5 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0); + attribute dont_merge : boolean; + attribute dont_merge of u0_m0_wo0_wi0_r0_delayr32_sticky_ena_q : signal is true; + signal u0_m0_wo0_wi0_r0_delayr32_rdmux_s : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_rdmux_q : STD_LOGIC_VECTOR (4 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_cmp_b : STD_LOGIC_VECTOR (5 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_cmp_q : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_notEnable_q : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_nor_q : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_wi0_r0_delayr32_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0); + signal u0_m0_wo0_wi0_r0_delayr33_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr34_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr35_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr36_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr37_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr38_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr39_q : STD_LOGIC_VECTOR (15 downto 0); + signal u0_m0_wo0_wi0_r0_delayr40_q : STD_LOGIC_VECTOR (15 downto 0); + signal out0_m0_wo0_lineup_select_delay_0_q : STD_LOGIC_VECTOR (0 downto 0); + signal out0_m0_wo0_assign_id3_q : STD_LOGIC_VECTOR (0 downto 0); + +begin + + + -- VCC(CONSTANT,1)@0 + VCC_q <= "1"; + + -- u0_m0_wo0_wi0_r0_delayr40(DELAY,59)@10 + u0_m0_wo0_wi0_r0_delayr40_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr39_q); + + -- u0_m0_wo0_wi0_r0_delayr39(DELAY,58)@10 + u0_m0_wo0_wi0_r0_delayr39_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr38_q); + + -- u0_m0_wo0_wi0_r0_delayr38(DELAY,57)@10 + u0_m0_wo0_wi0_r0_delayr38_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr37_q); + + -- u0_m0_wo0_wi0_r0_delayr37(DELAY,56)@10 + u0_m0_wo0_wi0_r0_delayr37_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr36_q); + + -- u0_m0_wo0_wi0_r0_delayr36(DELAY,55)@10 + u0_m0_wo0_wi0_r0_delayr36_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr35_q); + + -- u0_m0_wo0_wi0_r0_delayr35(DELAY,54)@10 + u0_m0_wo0_wi0_r0_delayr35_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr34_q); + + -- u0_m0_wo0_wi0_r0_delayr34(DELAY,53)@10 + u0_m0_wo0_wi0_r0_delayr34_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr33_q); + + -- u0_m0_wo0_wi0_r0_delayr33(DELAY,52)@10 + u0_m0_wo0_wi0_r0_delayr33_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr32_mem_q); + + -- u0_m0_wo0_wi0_r0_delayr32_notEnable(LOGICAL,122)@10 + u0_m0_wo0_wi0_r0_delayr32_notEnable_q <= STD_LOGIC_VECTOR(not (xIn_v)); + + -- u0_m0_wo0_wi0_r0_delayr32_nor(LOGICAL,123)@10 + u0_m0_wo0_wi0_r0_delayr32_nor_q <= not (u0_m0_wo0_wi0_r0_delayr32_notEnable_q or u0_m0_wo0_wi0_r0_delayr32_sticky_ena_q); + + -- u0_m0_wo0_wi0_r0_delayr32_mem_last(CONSTANT,119) + u0_m0_wo0_wi0_r0_delayr32_mem_last_q <= "011101"; + + -- u0_m0_wo0_wi0_r0_delayr32_cmp(LOGICAL,120)@10 + u0_m0_wo0_wi0_r0_delayr32_cmp_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_r0_delayr32_rdmux_q); + u0_m0_wo0_wi0_r0_delayr32_cmp_q <= "1" WHEN u0_m0_wo0_wi0_r0_delayr32_mem_last_q = u0_m0_wo0_wi0_r0_delayr32_cmp_b ELSE "0"; + + -- u0_m0_wo0_wi0_r0_delayr32_cmpReg(REG,121)@10 + 1 + u0_m0_wo0_wi0_r0_delayr32_cmpReg_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_wi0_r0_delayr32_cmpReg_q <= "0"; + ELSIF (clk'EVENT AND clk = '1') THEN + IF (xIn_v = "1") THEN + u0_m0_wo0_wi0_r0_delayr32_cmpReg_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr32_cmp_q); + END IF; + END IF; + END PROCESS; + + -- u0_m0_wo0_wi0_r0_delayr32_sticky_ena(REG,124)@10 + 1 + u0_m0_wo0_wi0_r0_delayr32_sticky_ena_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_wi0_r0_delayr32_sticky_ena_q <= "0"; + ELSIF (clk'EVENT AND clk = '1') THEN + IF (u0_m0_wo0_wi0_r0_delayr32_nor_q = "1") THEN + u0_m0_wo0_wi0_r0_delayr32_sticky_ena_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr32_cmpReg_q); + END IF; + END IF; + END PROCESS; + + -- u0_m0_wo0_wi0_r0_delayr32_enaAnd(LOGICAL,125)@10 + u0_m0_wo0_wi0_r0_delayr32_enaAnd_q <= u0_m0_wo0_wi0_r0_delayr32_sticky_ena_q and xIn_v; + + -- u0_m0_wo0_wi0_r0_delayr32_rdcnt(COUNTER,116)@10 + 1 + -- low=0, high=30, step=1, init=0 + u0_m0_wo0_wi0_r0_delayr32_rdcnt_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_wi0_r0_delayr32_rdcnt_i <= TO_UNSIGNED(0, 5); + u0_m0_wo0_wi0_r0_delayr32_rdcnt_eq <= '0'; + ELSIF (clk'EVENT AND clk = '1') THEN + IF (xIn_v = "1") THEN + IF (u0_m0_wo0_wi0_r0_delayr32_rdcnt_i = TO_UNSIGNED(29, 5)) THEN + u0_m0_wo0_wi0_r0_delayr32_rdcnt_eq <= '1'; + ELSE + u0_m0_wo0_wi0_r0_delayr32_rdcnt_eq <= '0'; + END IF; + IF (u0_m0_wo0_wi0_r0_delayr32_rdcnt_eq = '1') THEN + u0_m0_wo0_wi0_r0_delayr32_rdcnt_i <= u0_m0_wo0_wi0_r0_delayr32_rdcnt_i + 2; + ELSE + u0_m0_wo0_wi0_r0_delayr32_rdcnt_i <= u0_m0_wo0_wi0_r0_delayr32_rdcnt_i + 1; + END IF; + END IF; + END IF; + END PROCESS; + u0_m0_wo0_wi0_r0_delayr32_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_r0_delayr32_rdcnt_i, 5))); + + -- u0_m0_wo0_wi0_r0_delayr32_rdmux(MUX,117)@10 + u0_m0_wo0_wi0_r0_delayr32_rdmux_s <= xIn_v; + u0_m0_wo0_wi0_r0_delayr32_rdmux_combproc: PROCESS (u0_m0_wo0_wi0_r0_delayr32_rdmux_s, u0_m0_wo0_wi0_r0_delayr32_wraddr_q, u0_m0_wo0_wi0_r0_delayr32_rdcnt_q) + BEGIN + CASE (u0_m0_wo0_wi0_r0_delayr32_rdmux_s) IS + WHEN "0" => u0_m0_wo0_wi0_r0_delayr32_rdmux_q <= u0_m0_wo0_wi0_r0_delayr32_wraddr_q; + WHEN "1" => u0_m0_wo0_wi0_r0_delayr32_rdmux_q <= u0_m0_wo0_wi0_r0_delayr32_rdcnt_q; + WHEN OTHERS => u0_m0_wo0_wi0_r0_delayr32_rdmux_q <= (others => '0'); + END CASE; + END PROCESS; + + -- u0_m0_wo0_wi0_r0_delayr32_wraddr(REG,118)@10 + 1 + u0_m0_wo0_wi0_r0_delayr32_wraddr_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_wi0_r0_delayr32_wraddr_q <= "11110"; + ELSIF (clk'EVENT AND clk = '1') THEN + u0_m0_wo0_wi0_r0_delayr32_wraddr_q <= STD_LOGIC_VECTOR(u0_m0_wo0_wi0_r0_delayr32_rdmux_q); + END IF; + END PROCESS; + + -- u0_m0_wo0_wi0_r0_delayr32_mem(DUALMEM,115)@10 + 2 + u0_m0_wo0_wi0_r0_delayr32_mem_ia <= STD_LOGIC_VECTOR(xIn_0); + u0_m0_wo0_wi0_r0_delayr32_mem_aa <= u0_m0_wo0_wi0_r0_delayr32_wraddr_q; + u0_m0_wo0_wi0_r0_delayr32_mem_ab <= u0_m0_wo0_wi0_r0_delayr32_rdmux_q; + u0_m0_wo0_wi0_r0_delayr32_mem_reset0 <= areset; + u0_m0_wo0_wi0_r0_delayr32_mem_dmem : altera_syncram + GENERIC MAP ( + ram_block_type => "MLAB", + operation_mode => "DUAL_PORT", + width_a => 16, + widthad_a => 5, + numwords_a => 31, + width_b => 16, + widthad_b => 5, + numwords_b => 31, + lpm_type => "altera_syncram", + width_byteena_a => 1, + address_reg_b => "CLOCK0", + indata_reg_b => "CLOCK0", + rdcontrol_reg_b => "CLOCK0", + byteena_reg_b => "CLOCK0", + outdata_reg_b => "CLOCK1", + outdata_aclr_b => "CLEAR1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_b => "NORMAL", + read_during_write_mode_mixed_ports => "DONT_CARE", + power_up_uninitialized => "TRUE", + intended_device_family => "Cyclone V" + ) + PORT MAP ( + clocken1 => u0_m0_wo0_wi0_r0_delayr32_enaAnd_q(0), + clocken0 => VCC_q(0), + clock0 => clk, + aclr1 => u0_m0_wo0_wi0_r0_delayr32_mem_reset0, + clock1 => clk, + address_a => u0_m0_wo0_wi0_r0_delayr32_mem_aa, + data_a => u0_m0_wo0_wi0_r0_delayr32_mem_ia, + wren_a => xIn_v(0), + address_b => u0_m0_wo0_wi0_r0_delayr32_mem_ab, + q_b => u0_m0_wo0_wi0_r0_delayr32_mem_iq + ); + u0_m0_wo0_wi0_r0_delayr32_mem_q <= u0_m0_wo0_wi0_r0_delayr32_mem_iq(15 downto 0); + + -- d_u0_m0_wo0_compute_q_11(DELAY,113)@10 + 1 + d_u0_m0_wo0_compute_q_11 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => xIn_v, xout => d_u0_m0_wo0_compute_q_11_q, clk => clk, aclr => areset ); + + -- u0_m0_wo0_cma1(CHAINMULTADD,105)@10 + 2 + u0_m0_wo0_cma1_reset <= areset; + u0_m0_wo0_cma1_ena0 <= xIn_v(0); + u0_m0_wo0_cma1_ena1 <= d_u0_m0_wo0_compute_q_11_q(0); + -- altera synthesis_off + u0_m0_wo0_cma1_k0 <= ( + 0 => TO_SIGNED(5377,14), + others => (others => '0')); + u0_m0_wo0_cma1_k1 <= ( + 0 => TO_SIGNED(5360,14), + others => (others => '0')); + u0_m0_wo0_cma1_k2 <= ( + 0 => TO_SIGNED(4113,14), + others => (others => '0')); + u0_m0_wo0_cma1_k3 <= ( + 0 => TO_SIGNED(2350,14), + others => (others => '0')); + u0_m0_wo0_cma1_k4 <= ( + 0 => TO_SIGNED(712,14), + others => (others => '0')); + u0_m0_wo0_cma1_k5 <= ( + 0 => TO_SIGNED(-427,14), + others => (others => '0')); + u0_m0_wo0_cma1_k6 <= ( + 0 => TO_SIGNED(-1050,14), + others => (others => '0')); + u0_m0_wo0_cma1_k7 <= ( + 0 => TO_SIGNED(-1264,14), + others => (others => '0')); + u0_m0_wo0_cma1_k8 <= ( + 0 => TO_SIGNED(-1299,14), + others => (others => '0')); + u0_m0_wo0_cma1_k9 <= ( + others => (others => '0')); + -- altera synthesis_on + u0_m0_wo0_cma1_r(0) <= u0_m0_wo0_cma1_k0(TO_INTEGER(u0_m0_wo0_cma1_c0(0))); + u0_m0_wo0_cma1_r(1) <= u0_m0_wo0_cma1_k1(TO_INTEGER(u0_m0_wo0_cma1_c0(1))); + u0_m0_wo0_cma1_r(2) <= u0_m0_wo0_cma1_k2(TO_INTEGER(u0_m0_wo0_cma1_c0(2))); + u0_m0_wo0_cma1_r(3) <= u0_m0_wo0_cma1_k3(TO_INTEGER(u0_m0_wo0_cma1_c0(3))); + u0_m0_wo0_cma1_r(4) <= u0_m0_wo0_cma1_k4(TO_INTEGER(u0_m0_wo0_cma1_c0(4))); + u0_m0_wo0_cma1_r(5) <= u0_m0_wo0_cma1_k5(TO_INTEGER(u0_m0_wo0_cma1_c0(5))); + u0_m0_wo0_cma1_r(6) <= u0_m0_wo0_cma1_k6(TO_INTEGER(u0_m0_wo0_cma1_c0(6))); + u0_m0_wo0_cma1_r(7) <= u0_m0_wo0_cma1_k7(TO_INTEGER(u0_m0_wo0_cma1_c0(7))); + u0_m0_wo0_cma1_r(8) <= u0_m0_wo0_cma1_k8(TO_INTEGER(u0_m0_wo0_cma1_c0(8))); + u0_m0_wo0_cma1_r(9) <= u0_m0_wo0_cma1_k9(TO_INTEGER(u0_m0_wo0_cma1_c0(9))); + u0_m0_wo0_cma1_p(0) <= u0_m0_wo0_cma1_a0(0) * u0_m0_wo0_cma1_r(0); + u0_m0_wo0_cma1_p(1) <= u0_m0_wo0_cma1_a0(1) * u0_m0_wo0_cma1_r(1); + u0_m0_wo0_cma1_p(2) <= u0_m0_wo0_cma1_a0(2) * u0_m0_wo0_cma1_r(2); + u0_m0_wo0_cma1_p(3) <= u0_m0_wo0_cma1_a0(3) * u0_m0_wo0_cma1_r(3); + u0_m0_wo0_cma1_p(4) <= u0_m0_wo0_cma1_a0(4) * u0_m0_wo0_cma1_r(4); + u0_m0_wo0_cma1_p(5) <= u0_m0_wo0_cma1_a0(5) * u0_m0_wo0_cma1_r(5); + u0_m0_wo0_cma1_p(6) <= u0_m0_wo0_cma1_a0(6) * u0_m0_wo0_cma1_r(6); + u0_m0_wo0_cma1_p(7) <= u0_m0_wo0_cma1_a0(7) * u0_m0_wo0_cma1_r(7); + u0_m0_wo0_cma1_p(8) <= u0_m0_wo0_cma1_a0(8) * u0_m0_wo0_cma1_r(8); + u0_m0_wo0_cma1_p(9) <= u0_m0_wo0_cma1_a0(9) * u0_m0_wo0_cma1_r(9); + u0_m0_wo0_cma1_u(0) <= RESIZE(u0_m0_wo0_cma1_p(0),34); + u0_m0_wo0_cma1_u(1) <= RESIZE(u0_m0_wo0_cma1_p(1),34); + u0_m0_wo0_cma1_u(2) <= RESIZE(u0_m0_wo0_cma1_p(2),34); + u0_m0_wo0_cma1_u(3) <= RESIZE(u0_m0_wo0_cma1_p(3),34); + u0_m0_wo0_cma1_u(4) <= RESIZE(u0_m0_wo0_cma1_p(4),34); + u0_m0_wo0_cma1_u(5) <= RESIZE(u0_m0_wo0_cma1_p(5),34); + u0_m0_wo0_cma1_u(6) <= RESIZE(u0_m0_wo0_cma1_p(6),34); + u0_m0_wo0_cma1_u(7) <= RESIZE(u0_m0_wo0_cma1_p(7),34); + u0_m0_wo0_cma1_u(8) <= RESIZE(u0_m0_wo0_cma1_p(8),34); + u0_m0_wo0_cma1_u(9) <= RESIZE(u0_m0_wo0_cma1_p(9),34); + u0_m0_wo0_cma1_w(0) <= u0_m0_wo0_cma1_u(0); + u0_m0_wo0_cma1_w(1) <= u0_m0_wo0_cma1_u(1); + u0_m0_wo0_cma1_w(2) <= u0_m0_wo0_cma1_u(2); + u0_m0_wo0_cma1_w(3) <= u0_m0_wo0_cma1_u(3); + u0_m0_wo0_cma1_w(4) <= u0_m0_wo0_cma1_u(4); + u0_m0_wo0_cma1_w(5) <= u0_m0_wo0_cma1_u(5); + u0_m0_wo0_cma1_w(6) <= u0_m0_wo0_cma1_u(6); + u0_m0_wo0_cma1_w(7) <= u0_m0_wo0_cma1_u(7); + u0_m0_wo0_cma1_w(8) <= u0_m0_wo0_cma1_u(8); + u0_m0_wo0_cma1_w(9) <= u0_m0_wo0_cma1_u(9); + u0_m0_wo0_cma1_x(0) <= u0_m0_wo0_cma1_w(0); + u0_m0_wo0_cma1_x(1) <= u0_m0_wo0_cma1_w(1); + u0_m0_wo0_cma1_x(2) <= u0_m0_wo0_cma1_w(2); + u0_m0_wo0_cma1_x(3) <= u0_m0_wo0_cma1_w(3); + u0_m0_wo0_cma1_x(4) <= u0_m0_wo0_cma1_w(4); + u0_m0_wo0_cma1_x(5) <= u0_m0_wo0_cma1_w(5); + u0_m0_wo0_cma1_x(6) <= u0_m0_wo0_cma1_w(6); + u0_m0_wo0_cma1_x(7) <= u0_m0_wo0_cma1_w(7); + u0_m0_wo0_cma1_x(8) <= u0_m0_wo0_cma1_w(8); + u0_m0_wo0_cma1_x(9) <= u0_m0_wo0_cma1_w(9); + u0_m0_wo0_cma1_y(0) <= u0_m0_wo0_cma1_s(1) + u0_m0_wo0_cma1_x(0); + u0_m0_wo0_cma1_y(1) <= u0_m0_wo0_cma1_s(2) + u0_m0_wo0_cma1_x(1); + u0_m0_wo0_cma1_y(2) <= u0_m0_wo0_cma1_s(3) + u0_m0_wo0_cma1_x(2); + u0_m0_wo0_cma1_y(3) <= u0_m0_wo0_cma1_s(4) + u0_m0_wo0_cma1_x(3); + u0_m0_wo0_cma1_y(4) <= u0_m0_wo0_cma1_s(5) + u0_m0_wo0_cma1_x(4); + u0_m0_wo0_cma1_y(5) <= u0_m0_wo0_cma1_s(6) + u0_m0_wo0_cma1_x(5); + u0_m0_wo0_cma1_y(6) <= u0_m0_wo0_cma1_s(7) + u0_m0_wo0_cma1_x(6); + u0_m0_wo0_cma1_y(7) <= u0_m0_wo0_cma1_s(8) + u0_m0_wo0_cma1_x(7); + u0_m0_wo0_cma1_y(8) <= u0_m0_wo0_cma1_s(9) + u0_m0_wo0_cma1_x(8); + u0_m0_wo0_cma1_y(9) <= u0_m0_wo0_cma1_x(9); + u0_m0_wo0_cma1_chainmultadd_input: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_cma1_a0 <= (others => (others => '0')); + u0_m0_wo0_cma1_c0 <= (others => (others => '0')); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (u0_m0_wo0_cma1_ena0 = '1') THEN + u0_m0_wo0_cma1_a0(0) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr32_mem_q),16); + u0_m0_wo0_cma1_a0(1) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr33_q),16); + u0_m0_wo0_cma1_a0(2) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr34_q),16); + u0_m0_wo0_cma1_a0(3) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr35_q),16); + u0_m0_wo0_cma1_a0(4) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr36_q),16); + u0_m0_wo0_cma1_a0(5) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr37_q),16); + u0_m0_wo0_cma1_a0(6) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr38_q),16); + u0_m0_wo0_cma1_a0(7) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr39_q),16); + u0_m0_wo0_cma1_a0(8) <= RESIZE(SIGNED(u0_m0_wo0_wi0_r0_delayr40_q),16); + u0_m0_wo0_cma1_a0(9) <= (others => '0'); + u0_m0_wo0_cma1_c0(0) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(1) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(2) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(3) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(4) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(5) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(6) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(7) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(8) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma1_c0(9) <= (others => '0'); + END IF; + END IF; + END PROCESS; + u0_m0_wo0_cma1_chainmultadd_output: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_cma1_s <= (others => (others => '0')); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (u0_m0_wo0_cma1_ena1 = '1') THEN + u0_m0_wo0_cma1_s(0) <= u0_m0_wo0_cma1_y(0); + u0_m0_wo0_cma1_s(1) <= u0_m0_wo0_cma1_y(1); + u0_m0_wo0_cma1_s(2) <= u0_m0_wo0_cma1_y(2); + u0_m0_wo0_cma1_s(3) <= u0_m0_wo0_cma1_y(3); + u0_m0_wo0_cma1_s(4) <= u0_m0_wo0_cma1_y(4); + u0_m0_wo0_cma1_s(5) <= u0_m0_wo0_cma1_y(5); + u0_m0_wo0_cma1_s(6) <= u0_m0_wo0_cma1_y(6); + u0_m0_wo0_cma1_s(7) <= u0_m0_wo0_cma1_y(7); + u0_m0_wo0_cma1_s(8) <= u0_m0_wo0_cma1_y(8); + u0_m0_wo0_cma1_s(9) <= u0_m0_wo0_cma1_y(9); + END IF; + END IF; + END PROCESS; + u0_m0_wo0_cma1_delay : dspba_delay + GENERIC MAP ( width => 34, depth => 0, reset_kind => "ASYNC" ) + PORT MAP ( xin => STD_LOGIC_VECTOR(u0_m0_wo0_cma1_s(0)(33 downto 0)), xout => u0_m0_wo0_cma1_qq, clk => clk, aclr => areset ); + u0_m0_wo0_cma1_q <= STD_LOGIC_VECTOR(u0_m0_wo0_cma1_qq(33 downto 0)); + + -- u0_m0_wo0_cma0(CHAINMULTADD,104)@10 + 2 + u0_m0_wo0_cma0_reset <= areset; + u0_m0_wo0_cma0_ena0 <= xIn_v(0); + u0_m0_wo0_cma0_ena1 <= d_u0_m0_wo0_compute_q_11_q(0); + -- altera synthesis_off + u0_m0_wo0_cma0_k0 <= ( + 0 => TO_SIGNED(-1299,15), + others => (others => '0')); + u0_m0_wo0_cma0_k1 <= ( + 0 => TO_SIGNED(-1264,15), + others => (others => '0')); + u0_m0_wo0_cma0_k2 <= ( + 0 => TO_SIGNED(-1050,15), + others => (others => '0')); + u0_m0_wo0_cma0_k3 <= ( + 0 => TO_SIGNED(-427,15), + others => (others => '0')); + u0_m0_wo0_cma0_k4 <= ( + 0 => TO_SIGNED(712,15), + others => (others => '0')); + u0_m0_wo0_cma0_k5 <= ( + 0 => TO_SIGNED(2350,15), + others => (others => '0')); + u0_m0_wo0_cma0_k6 <= ( + 0 => TO_SIGNED(4113,15), + others => (others => '0')); + u0_m0_wo0_cma0_k7 <= ( + 0 => TO_SIGNED(5360,15), + others => (others => '0')); + u0_m0_wo0_cma0_k8 <= ( + 0 => TO_SIGNED(5377,15), + others => (others => '0')); + u0_m0_wo0_cma0_k9 <= ( + 0 => TO_SIGNED(3686,15), + others => (others => '0')); + u0_m0_wo0_cma0_k10 <= ( + 0 => TO_SIGNED(267,15), + others => (others => '0')); + u0_m0_wo0_cma0_k11 <= ( + 0 => TO_SIGNED(-4309,15), + others => (others => '0')); + u0_m0_wo0_cma0_k12 <= ( + 0 => TO_SIGNED(-8868,15), + others => (others => '0')); + u0_m0_wo0_cma0_k13 <= ( + 0 => TO_SIGNED(-12055,15), + others => (others => '0')); + u0_m0_wo0_cma0_k14 <= ( + 0 => TO_SIGNED(-12679,15), + others => (others => '0')); + u0_m0_wo0_cma0_k15 <= ( + 0 => TO_SIGNED(-10168,15), + others => (others => '0')); + u0_m0_wo0_cma0_k16 <= ( + 0 => TO_SIGNED(-4790,15), + others => (others => '0')); + u0_m0_wo0_cma0_k17 <= ( + 0 => TO_SIGNED(2297,15), + others => (others => '0')); + u0_m0_wo0_cma0_k18 <= ( + 0 => TO_SIGNED(9348,15), + others => (others => '0')); + u0_m0_wo0_cma0_k19 <= ( + 0 => TO_SIGNED(14495,15), + others => (others => '0')); + u0_m0_wo0_cma0_k20 <= ( + 0 => TO_SIGNED(16382,15), + others => (others => '0')); + u0_m0_wo0_cma0_k21 <= ( + 0 => TO_SIGNED(14495,15), + others => (others => '0')); + u0_m0_wo0_cma0_k22 <= ( + 0 => TO_SIGNED(9348,15), + others => (others => '0')); + u0_m0_wo0_cma0_k23 <= ( + 0 => TO_SIGNED(2297,15), + others => (others => '0')); + u0_m0_wo0_cma0_k24 <= ( + 0 => TO_SIGNED(-4790,15), + others => (others => '0')); + u0_m0_wo0_cma0_k25 <= ( + 0 => TO_SIGNED(-10168,15), + others => (others => '0')); + u0_m0_wo0_cma0_k26 <= ( + 0 => TO_SIGNED(-12679,15), + others => (others => '0')); + u0_m0_wo0_cma0_k27 <= ( + 0 => TO_SIGNED(-12055,15), + others => (others => '0')); + u0_m0_wo0_cma0_k28 <= ( + 0 => TO_SIGNED(-8868,15), + others => (others => '0')); + u0_m0_wo0_cma0_k29 <= ( + 0 => TO_SIGNED(-4309,15), + others => (others => '0')); + u0_m0_wo0_cma0_k30 <= ( + 0 => TO_SIGNED(267,15), + others => (others => '0')); + u0_m0_wo0_cma0_k31 <= ( + 0 => TO_SIGNED(3686,15), + others => (others => '0')); + -- altera synthesis_on + u0_m0_wo0_cma0_r(0) <= u0_m0_wo0_cma0_k0(TO_INTEGER(u0_m0_wo0_cma0_c0(0))); + u0_m0_wo0_cma0_r(1) <= u0_m0_wo0_cma0_k1(TO_INTEGER(u0_m0_wo0_cma0_c0(1))); + u0_m0_wo0_cma0_r(2) <= u0_m0_wo0_cma0_k2(TO_INTEGER(u0_m0_wo0_cma0_c0(2))); + u0_m0_wo0_cma0_r(3) <= u0_m0_wo0_cma0_k3(TO_INTEGER(u0_m0_wo0_cma0_c0(3))); + u0_m0_wo0_cma0_r(4) <= u0_m0_wo0_cma0_k4(TO_INTEGER(u0_m0_wo0_cma0_c0(4))); + u0_m0_wo0_cma0_r(5) <= u0_m0_wo0_cma0_k5(TO_INTEGER(u0_m0_wo0_cma0_c0(5))); + u0_m0_wo0_cma0_r(6) <= u0_m0_wo0_cma0_k6(TO_INTEGER(u0_m0_wo0_cma0_c0(6))); + u0_m0_wo0_cma0_r(7) <= u0_m0_wo0_cma0_k7(TO_INTEGER(u0_m0_wo0_cma0_c0(7))); + u0_m0_wo0_cma0_r(8) <= u0_m0_wo0_cma0_k8(TO_INTEGER(u0_m0_wo0_cma0_c0(8))); + u0_m0_wo0_cma0_r(9) <= u0_m0_wo0_cma0_k9(TO_INTEGER(u0_m0_wo0_cma0_c0(9))); + u0_m0_wo0_cma0_r(10) <= u0_m0_wo0_cma0_k10(TO_INTEGER(u0_m0_wo0_cma0_c0(10))); + u0_m0_wo0_cma0_r(11) <= u0_m0_wo0_cma0_k11(TO_INTEGER(u0_m0_wo0_cma0_c0(11))); + u0_m0_wo0_cma0_r(12) <= u0_m0_wo0_cma0_k12(TO_INTEGER(u0_m0_wo0_cma0_c0(12))); + u0_m0_wo0_cma0_r(13) <= u0_m0_wo0_cma0_k13(TO_INTEGER(u0_m0_wo0_cma0_c0(13))); + u0_m0_wo0_cma0_r(14) <= u0_m0_wo0_cma0_k14(TO_INTEGER(u0_m0_wo0_cma0_c0(14))); + u0_m0_wo0_cma0_r(15) <= u0_m0_wo0_cma0_k15(TO_INTEGER(u0_m0_wo0_cma0_c0(15))); + u0_m0_wo0_cma0_r(16) <= u0_m0_wo0_cma0_k16(TO_INTEGER(u0_m0_wo0_cma0_c0(16))); + u0_m0_wo0_cma0_r(17) <= u0_m0_wo0_cma0_k17(TO_INTEGER(u0_m0_wo0_cma0_c0(17))); + u0_m0_wo0_cma0_r(18) <= u0_m0_wo0_cma0_k18(TO_INTEGER(u0_m0_wo0_cma0_c0(18))); + u0_m0_wo0_cma0_r(19) <= u0_m0_wo0_cma0_k19(TO_INTEGER(u0_m0_wo0_cma0_c0(19))); + u0_m0_wo0_cma0_r(20) <= u0_m0_wo0_cma0_k20(TO_INTEGER(u0_m0_wo0_cma0_c0(20))); + u0_m0_wo0_cma0_r(21) <= u0_m0_wo0_cma0_k21(TO_INTEGER(u0_m0_wo0_cma0_c0(21))); + u0_m0_wo0_cma0_r(22) <= u0_m0_wo0_cma0_k22(TO_INTEGER(u0_m0_wo0_cma0_c0(22))); + u0_m0_wo0_cma0_r(23) <= u0_m0_wo0_cma0_k23(TO_INTEGER(u0_m0_wo0_cma0_c0(23))); + u0_m0_wo0_cma0_r(24) <= u0_m0_wo0_cma0_k24(TO_INTEGER(u0_m0_wo0_cma0_c0(24))); + u0_m0_wo0_cma0_r(25) <= u0_m0_wo0_cma0_k25(TO_INTEGER(u0_m0_wo0_cma0_c0(25))); + u0_m0_wo0_cma0_r(26) <= u0_m0_wo0_cma0_k26(TO_INTEGER(u0_m0_wo0_cma0_c0(26))); + u0_m0_wo0_cma0_r(27) <= u0_m0_wo0_cma0_k27(TO_INTEGER(u0_m0_wo0_cma0_c0(27))); + u0_m0_wo0_cma0_r(28) <= u0_m0_wo0_cma0_k28(TO_INTEGER(u0_m0_wo0_cma0_c0(28))); + u0_m0_wo0_cma0_r(29) <= u0_m0_wo0_cma0_k29(TO_INTEGER(u0_m0_wo0_cma0_c0(29))); + u0_m0_wo0_cma0_r(30) <= u0_m0_wo0_cma0_k30(TO_INTEGER(u0_m0_wo0_cma0_c0(30))); + u0_m0_wo0_cma0_r(31) <= u0_m0_wo0_cma0_k31(TO_INTEGER(u0_m0_wo0_cma0_c0(31))); + u0_m0_wo0_cma0_p(0) <= u0_m0_wo0_cma0_a0(0) * u0_m0_wo0_cma0_r(0); + u0_m0_wo0_cma0_p(1) <= u0_m0_wo0_cma0_a0(1) * u0_m0_wo0_cma0_r(1); + u0_m0_wo0_cma0_p(2) <= u0_m0_wo0_cma0_a0(2) * u0_m0_wo0_cma0_r(2); + u0_m0_wo0_cma0_p(3) <= u0_m0_wo0_cma0_a0(3) * u0_m0_wo0_cma0_r(3); + u0_m0_wo0_cma0_p(4) <= u0_m0_wo0_cma0_a0(4) * u0_m0_wo0_cma0_r(4); + u0_m0_wo0_cma0_p(5) <= u0_m0_wo0_cma0_a0(5) * u0_m0_wo0_cma0_r(5); + u0_m0_wo0_cma0_p(6) <= u0_m0_wo0_cma0_a0(6) * u0_m0_wo0_cma0_r(6); + u0_m0_wo0_cma0_p(7) <= u0_m0_wo0_cma0_a0(7) * u0_m0_wo0_cma0_r(7); + u0_m0_wo0_cma0_p(8) <= u0_m0_wo0_cma0_a0(8) * u0_m0_wo0_cma0_r(8); + u0_m0_wo0_cma0_p(9) <= u0_m0_wo0_cma0_a0(9) * u0_m0_wo0_cma0_r(9); + u0_m0_wo0_cma0_p(10) <= u0_m0_wo0_cma0_a0(10) * u0_m0_wo0_cma0_r(10); + u0_m0_wo0_cma0_p(11) <= u0_m0_wo0_cma0_a0(11) * u0_m0_wo0_cma0_r(11); + u0_m0_wo0_cma0_p(12) <= u0_m0_wo0_cma0_a0(12) * u0_m0_wo0_cma0_r(12); + u0_m0_wo0_cma0_p(13) <= u0_m0_wo0_cma0_a0(13) * u0_m0_wo0_cma0_r(13); + u0_m0_wo0_cma0_p(14) <= u0_m0_wo0_cma0_a0(14) * u0_m0_wo0_cma0_r(14); + u0_m0_wo0_cma0_p(15) <= u0_m0_wo0_cma0_a0(15) * u0_m0_wo0_cma0_r(15); + u0_m0_wo0_cma0_p(16) <= u0_m0_wo0_cma0_a0(16) * u0_m0_wo0_cma0_r(16); + u0_m0_wo0_cma0_p(17) <= u0_m0_wo0_cma0_a0(17) * u0_m0_wo0_cma0_r(17); + u0_m0_wo0_cma0_p(18) <= u0_m0_wo0_cma0_a0(18) * u0_m0_wo0_cma0_r(18); + u0_m0_wo0_cma0_p(19) <= u0_m0_wo0_cma0_a0(19) * u0_m0_wo0_cma0_r(19); + u0_m0_wo0_cma0_p(20) <= u0_m0_wo0_cma0_a0(20) * u0_m0_wo0_cma0_r(20); + u0_m0_wo0_cma0_p(21) <= u0_m0_wo0_cma0_a0(21) * u0_m0_wo0_cma0_r(21); + u0_m0_wo0_cma0_p(22) <= u0_m0_wo0_cma0_a0(22) * u0_m0_wo0_cma0_r(22); + u0_m0_wo0_cma0_p(23) <= u0_m0_wo0_cma0_a0(23) * u0_m0_wo0_cma0_r(23); + u0_m0_wo0_cma0_p(24) <= u0_m0_wo0_cma0_a0(24) * u0_m0_wo0_cma0_r(24); + u0_m0_wo0_cma0_p(25) <= u0_m0_wo0_cma0_a0(25) * u0_m0_wo0_cma0_r(25); + u0_m0_wo0_cma0_p(26) <= u0_m0_wo0_cma0_a0(26) * u0_m0_wo0_cma0_r(26); + u0_m0_wo0_cma0_p(27) <= u0_m0_wo0_cma0_a0(27) * u0_m0_wo0_cma0_r(27); + u0_m0_wo0_cma0_p(28) <= u0_m0_wo0_cma0_a0(28) * u0_m0_wo0_cma0_r(28); + u0_m0_wo0_cma0_p(29) <= u0_m0_wo0_cma0_a0(29) * u0_m0_wo0_cma0_r(29); + u0_m0_wo0_cma0_p(30) <= u0_m0_wo0_cma0_a0(30) * u0_m0_wo0_cma0_r(30); + u0_m0_wo0_cma0_p(31) <= u0_m0_wo0_cma0_a0(31) * u0_m0_wo0_cma0_r(31); + u0_m0_wo0_cma0_u(0) <= RESIZE(u0_m0_wo0_cma0_p(0),36); + u0_m0_wo0_cma0_u(1) <= RESIZE(u0_m0_wo0_cma0_p(1),36); + u0_m0_wo0_cma0_u(2) <= RESIZE(u0_m0_wo0_cma0_p(2),36); + u0_m0_wo0_cma0_u(3) <= RESIZE(u0_m0_wo0_cma0_p(3),36); + u0_m0_wo0_cma0_u(4) <= RESIZE(u0_m0_wo0_cma0_p(4),36); + u0_m0_wo0_cma0_u(5) <= RESIZE(u0_m0_wo0_cma0_p(5),36); + u0_m0_wo0_cma0_u(6) <= RESIZE(u0_m0_wo0_cma0_p(6),36); + u0_m0_wo0_cma0_u(7) <= RESIZE(u0_m0_wo0_cma0_p(7),36); + u0_m0_wo0_cma0_u(8) <= RESIZE(u0_m0_wo0_cma0_p(8),36); + u0_m0_wo0_cma0_u(9) <= RESIZE(u0_m0_wo0_cma0_p(9),36); + u0_m0_wo0_cma0_u(10) <= RESIZE(u0_m0_wo0_cma0_p(10),36); + u0_m0_wo0_cma0_u(11) <= RESIZE(u0_m0_wo0_cma0_p(11),36); + u0_m0_wo0_cma0_u(12) <= RESIZE(u0_m0_wo0_cma0_p(12),36); + u0_m0_wo0_cma0_u(13) <= RESIZE(u0_m0_wo0_cma0_p(13),36); + u0_m0_wo0_cma0_u(14) <= RESIZE(u0_m0_wo0_cma0_p(14),36); + u0_m0_wo0_cma0_u(15) <= RESIZE(u0_m0_wo0_cma0_p(15),36); + u0_m0_wo0_cma0_u(16) <= RESIZE(u0_m0_wo0_cma0_p(16),36); + u0_m0_wo0_cma0_u(17) <= RESIZE(u0_m0_wo0_cma0_p(17),36); + u0_m0_wo0_cma0_u(18) <= RESIZE(u0_m0_wo0_cma0_p(18),36); + u0_m0_wo0_cma0_u(19) <= RESIZE(u0_m0_wo0_cma0_p(19),36); + u0_m0_wo0_cma0_u(20) <= RESIZE(u0_m0_wo0_cma0_p(20),36); + u0_m0_wo0_cma0_u(21) <= RESIZE(u0_m0_wo0_cma0_p(21),36); + u0_m0_wo0_cma0_u(22) <= RESIZE(u0_m0_wo0_cma0_p(22),36); + u0_m0_wo0_cma0_u(23) <= RESIZE(u0_m0_wo0_cma0_p(23),36); + u0_m0_wo0_cma0_u(24) <= RESIZE(u0_m0_wo0_cma0_p(24),36); + u0_m0_wo0_cma0_u(25) <= RESIZE(u0_m0_wo0_cma0_p(25),36); + u0_m0_wo0_cma0_u(26) <= RESIZE(u0_m0_wo0_cma0_p(26),36); + u0_m0_wo0_cma0_u(27) <= RESIZE(u0_m0_wo0_cma0_p(27),36); + u0_m0_wo0_cma0_u(28) <= RESIZE(u0_m0_wo0_cma0_p(28),36); + u0_m0_wo0_cma0_u(29) <= RESIZE(u0_m0_wo0_cma0_p(29),36); + u0_m0_wo0_cma0_u(30) <= RESIZE(u0_m0_wo0_cma0_p(30),36); + u0_m0_wo0_cma0_u(31) <= RESIZE(u0_m0_wo0_cma0_p(31),36); + u0_m0_wo0_cma0_w(0) <= u0_m0_wo0_cma0_u(0); + u0_m0_wo0_cma0_w(1) <= u0_m0_wo0_cma0_u(1); + u0_m0_wo0_cma0_w(2) <= u0_m0_wo0_cma0_u(2); + u0_m0_wo0_cma0_w(3) <= u0_m0_wo0_cma0_u(3); + u0_m0_wo0_cma0_w(4) <= u0_m0_wo0_cma0_u(4); + u0_m0_wo0_cma0_w(5) <= u0_m0_wo0_cma0_u(5); + u0_m0_wo0_cma0_w(6) <= u0_m0_wo0_cma0_u(6); + u0_m0_wo0_cma0_w(7) <= u0_m0_wo0_cma0_u(7); + u0_m0_wo0_cma0_w(8) <= u0_m0_wo0_cma0_u(8); + u0_m0_wo0_cma0_w(9) <= u0_m0_wo0_cma0_u(9); + u0_m0_wo0_cma0_w(10) <= u0_m0_wo0_cma0_u(10); + u0_m0_wo0_cma0_w(11) <= u0_m0_wo0_cma0_u(11); + u0_m0_wo0_cma0_w(12) <= u0_m0_wo0_cma0_u(12); + u0_m0_wo0_cma0_w(13) <= u0_m0_wo0_cma0_u(13); + u0_m0_wo0_cma0_w(14) <= u0_m0_wo0_cma0_u(14); + u0_m0_wo0_cma0_w(15) <= u0_m0_wo0_cma0_u(15); + u0_m0_wo0_cma0_w(16) <= u0_m0_wo0_cma0_u(16); + u0_m0_wo0_cma0_w(17) <= u0_m0_wo0_cma0_u(17); + u0_m0_wo0_cma0_w(18) <= u0_m0_wo0_cma0_u(18); + u0_m0_wo0_cma0_w(19) <= u0_m0_wo0_cma0_u(19); + u0_m0_wo0_cma0_w(20) <= u0_m0_wo0_cma0_u(20); + u0_m0_wo0_cma0_w(21) <= u0_m0_wo0_cma0_u(21); + u0_m0_wo0_cma0_w(22) <= u0_m0_wo0_cma0_u(22); + u0_m0_wo0_cma0_w(23) <= u0_m0_wo0_cma0_u(23); + u0_m0_wo0_cma0_w(24) <= u0_m0_wo0_cma0_u(24); + u0_m0_wo0_cma0_w(25) <= u0_m0_wo0_cma0_u(25); + u0_m0_wo0_cma0_w(26) <= u0_m0_wo0_cma0_u(26); + u0_m0_wo0_cma0_w(27) <= u0_m0_wo0_cma0_u(27); + u0_m0_wo0_cma0_w(28) <= u0_m0_wo0_cma0_u(28); + u0_m0_wo0_cma0_w(29) <= u0_m0_wo0_cma0_u(29); + u0_m0_wo0_cma0_w(30) <= u0_m0_wo0_cma0_u(30); + u0_m0_wo0_cma0_w(31) <= u0_m0_wo0_cma0_u(31); + u0_m0_wo0_cma0_x(0) <= u0_m0_wo0_cma0_w(0); + u0_m0_wo0_cma0_x(1) <= u0_m0_wo0_cma0_w(1); + u0_m0_wo0_cma0_x(2) <= u0_m0_wo0_cma0_w(2); + u0_m0_wo0_cma0_x(3) <= u0_m0_wo0_cma0_w(3); + u0_m0_wo0_cma0_x(4) <= u0_m0_wo0_cma0_w(4); + u0_m0_wo0_cma0_x(5) <= u0_m0_wo0_cma0_w(5); + u0_m0_wo0_cma0_x(6) <= u0_m0_wo0_cma0_w(6); + u0_m0_wo0_cma0_x(7) <= u0_m0_wo0_cma0_w(7); + u0_m0_wo0_cma0_x(8) <= u0_m0_wo0_cma0_w(8); + u0_m0_wo0_cma0_x(9) <= u0_m0_wo0_cma0_w(9); + u0_m0_wo0_cma0_x(10) <= u0_m0_wo0_cma0_w(10); + u0_m0_wo0_cma0_x(11) <= u0_m0_wo0_cma0_w(11); + u0_m0_wo0_cma0_x(12) <= u0_m0_wo0_cma0_w(12); + u0_m0_wo0_cma0_x(13) <= u0_m0_wo0_cma0_w(13); + u0_m0_wo0_cma0_x(14) <= u0_m0_wo0_cma0_w(14); + u0_m0_wo0_cma0_x(15) <= u0_m0_wo0_cma0_w(15); + u0_m0_wo0_cma0_x(16) <= u0_m0_wo0_cma0_w(16); + u0_m0_wo0_cma0_x(17) <= u0_m0_wo0_cma0_w(17); + u0_m0_wo0_cma0_x(18) <= u0_m0_wo0_cma0_w(18); + u0_m0_wo0_cma0_x(19) <= u0_m0_wo0_cma0_w(19); + u0_m0_wo0_cma0_x(20) <= u0_m0_wo0_cma0_w(20); + u0_m0_wo0_cma0_x(21) <= u0_m0_wo0_cma0_w(21); + u0_m0_wo0_cma0_x(22) <= u0_m0_wo0_cma0_w(22); + u0_m0_wo0_cma0_x(23) <= u0_m0_wo0_cma0_w(23); + u0_m0_wo0_cma0_x(24) <= u0_m0_wo0_cma0_w(24); + u0_m0_wo0_cma0_x(25) <= u0_m0_wo0_cma0_w(25); + u0_m0_wo0_cma0_x(26) <= u0_m0_wo0_cma0_w(26); + u0_m0_wo0_cma0_x(27) <= u0_m0_wo0_cma0_w(27); + u0_m0_wo0_cma0_x(28) <= u0_m0_wo0_cma0_w(28); + u0_m0_wo0_cma0_x(29) <= u0_m0_wo0_cma0_w(29); + u0_m0_wo0_cma0_x(30) <= u0_m0_wo0_cma0_w(30); + u0_m0_wo0_cma0_x(31) <= u0_m0_wo0_cma0_w(31); + u0_m0_wo0_cma0_y(0) <= u0_m0_wo0_cma0_s(1) + u0_m0_wo0_cma0_x(0); + u0_m0_wo0_cma0_y(1) <= u0_m0_wo0_cma0_s(2) + u0_m0_wo0_cma0_x(1); + u0_m0_wo0_cma0_y(2) <= u0_m0_wo0_cma0_s(3) + u0_m0_wo0_cma0_x(2); + u0_m0_wo0_cma0_y(3) <= u0_m0_wo0_cma0_s(4) + u0_m0_wo0_cma0_x(3); + u0_m0_wo0_cma0_y(4) <= u0_m0_wo0_cma0_s(5) + u0_m0_wo0_cma0_x(4); + u0_m0_wo0_cma0_y(5) <= u0_m0_wo0_cma0_s(6) + u0_m0_wo0_cma0_x(5); + u0_m0_wo0_cma0_y(6) <= u0_m0_wo0_cma0_s(7) + u0_m0_wo0_cma0_x(6); + u0_m0_wo0_cma0_y(7) <= u0_m0_wo0_cma0_s(8) + u0_m0_wo0_cma0_x(7); + u0_m0_wo0_cma0_y(8) <= u0_m0_wo0_cma0_s(9) + u0_m0_wo0_cma0_x(8); + u0_m0_wo0_cma0_y(9) <= u0_m0_wo0_cma0_s(10) + u0_m0_wo0_cma0_x(9); + u0_m0_wo0_cma0_y(10) <= u0_m0_wo0_cma0_s(11) + u0_m0_wo0_cma0_x(10); + u0_m0_wo0_cma0_y(11) <= u0_m0_wo0_cma0_s(12) + u0_m0_wo0_cma0_x(11); + u0_m0_wo0_cma0_y(12) <= u0_m0_wo0_cma0_s(13) + u0_m0_wo0_cma0_x(12); + u0_m0_wo0_cma0_y(13) <= u0_m0_wo0_cma0_s(14) + u0_m0_wo0_cma0_x(13); + u0_m0_wo0_cma0_y(14) <= u0_m0_wo0_cma0_s(15) + u0_m0_wo0_cma0_x(14); + u0_m0_wo0_cma0_y(15) <= u0_m0_wo0_cma0_s(16) + u0_m0_wo0_cma0_x(15); + u0_m0_wo0_cma0_y(16) <= u0_m0_wo0_cma0_s(17) + u0_m0_wo0_cma0_x(16); + u0_m0_wo0_cma0_y(17) <= u0_m0_wo0_cma0_s(18) + u0_m0_wo0_cma0_x(17); + u0_m0_wo0_cma0_y(18) <= u0_m0_wo0_cma0_s(19) + u0_m0_wo0_cma0_x(18); + u0_m0_wo0_cma0_y(19) <= u0_m0_wo0_cma0_s(20) + u0_m0_wo0_cma0_x(19); + u0_m0_wo0_cma0_y(20) <= u0_m0_wo0_cma0_s(21) + u0_m0_wo0_cma0_x(20); + u0_m0_wo0_cma0_y(21) <= u0_m0_wo0_cma0_s(22) + u0_m0_wo0_cma0_x(21); + u0_m0_wo0_cma0_y(22) <= u0_m0_wo0_cma0_s(23) + u0_m0_wo0_cma0_x(22); + u0_m0_wo0_cma0_y(23) <= u0_m0_wo0_cma0_s(24) + u0_m0_wo0_cma0_x(23); + u0_m0_wo0_cma0_y(24) <= u0_m0_wo0_cma0_s(25) + u0_m0_wo0_cma0_x(24); + u0_m0_wo0_cma0_y(25) <= u0_m0_wo0_cma0_s(26) + u0_m0_wo0_cma0_x(25); + u0_m0_wo0_cma0_y(26) <= u0_m0_wo0_cma0_s(27) + u0_m0_wo0_cma0_x(26); + u0_m0_wo0_cma0_y(27) <= u0_m0_wo0_cma0_s(28) + u0_m0_wo0_cma0_x(27); + u0_m0_wo0_cma0_y(28) <= u0_m0_wo0_cma0_s(29) + u0_m0_wo0_cma0_x(28); + u0_m0_wo0_cma0_y(29) <= u0_m0_wo0_cma0_s(30) + u0_m0_wo0_cma0_x(29); + u0_m0_wo0_cma0_y(30) <= u0_m0_wo0_cma0_s(31) + u0_m0_wo0_cma0_x(30); + u0_m0_wo0_cma0_y(31) <= u0_m0_wo0_cma0_x(31); + u0_m0_wo0_cma0_chainmultadd_input: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_cma0_a0 <= (others => (others => '0')); + u0_m0_wo0_cma0_c0 <= (others => (others => '0')); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (u0_m0_wo0_cma0_ena0 = '1') THEN + u0_m0_wo0_cma0_a0(0) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(1) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(2) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(3) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(4) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(5) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(6) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(7) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(8) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(9) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(10) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(11) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(12) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(13) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(14) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(15) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(16) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(17) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(18) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(19) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(20) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(21) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(22) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(23) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(24) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(25) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(26) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(27) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(28) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(29) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(30) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_a0(31) <= RESIZE(SIGNED(xIn_0),16); + u0_m0_wo0_cma0_c0(0) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(1) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(2) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(3) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(4) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(5) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(6) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(7) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(8) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(9) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(10) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(11) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(12) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(13) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(14) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(15) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(16) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(17) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(18) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(19) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(20) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(21) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(22) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(23) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(24) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(25) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(26) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(27) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(28) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(29) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(30) <= RESIZE(UNSIGNED(GND_q),3); + u0_m0_wo0_cma0_c0(31) <= RESIZE(UNSIGNED(GND_q),3); + END IF; + END IF; + END PROCESS; + u0_m0_wo0_cma0_chainmultadd_output: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_cma0_s <= (others => (others => '0')); + ELSIF (clk'EVENT AND clk = '1') THEN + IF (u0_m0_wo0_cma0_ena1 = '1') THEN + u0_m0_wo0_cma0_s(0) <= u0_m0_wo0_cma0_y(0); + u0_m0_wo0_cma0_s(1) <= u0_m0_wo0_cma0_y(1); + u0_m0_wo0_cma0_s(2) <= u0_m0_wo0_cma0_y(2); + u0_m0_wo0_cma0_s(3) <= u0_m0_wo0_cma0_y(3); + u0_m0_wo0_cma0_s(4) <= u0_m0_wo0_cma0_y(4); + u0_m0_wo0_cma0_s(5) <= u0_m0_wo0_cma0_y(5); + u0_m0_wo0_cma0_s(6) <= u0_m0_wo0_cma0_y(6); + u0_m0_wo0_cma0_s(7) <= u0_m0_wo0_cma0_y(7); + u0_m0_wo0_cma0_s(8) <= u0_m0_wo0_cma0_y(8); + u0_m0_wo0_cma0_s(9) <= u0_m0_wo0_cma0_y(9); + u0_m0_wo0_cma0_s(10) <= u0_m0_wo0_cma0_y(10); + u0_m0_wo0_cma0_s(11) <= u0_m0_wo0_cma0_y(11); + u0_m0_wo0_cma0_s(12) <= u0_m0_wo0_cma0_y(12); + u0_m0_wo0_cma0_s(13) <= u0_m0_wo0_cma0_y(13); + u0_m0_wo0_cma0_s(14) <= u0_m0_wo0_cma0_y(14); + u0_m0_wo0_cma0_s(15) <= u0_m0_wo0_cma0_y(15); + u0_m0_wo0_cma0_s(16) <= u0_m0_wo0_cma0_y(16); + u0_m0_wo0_cma0_s(17) <= u0_m0_wo0_cma0_y(17); + u0_m0_wo0_cma0_s(18) <= u0_m0_wo0_cma0_y(18); + u0_m0_wo0_cma0_s(19) <= u0_m0_wo0_cma0_y(19); + u0_m0_wo0_cma0_s(20) <= u0_m0_wo0_cma0_y(20); + u0_m0_wo0_cma0_s(21) <= u0_m0_wo0_cma0_y(21); + u0_m0_wo0_cma0_s(22) <= u0_m0_wo0_cma0_y(22); + u0_m0_wo0_cma0_s(23) <= u0_m0_wo0_cma0_y(23); + u0_m0_wo0_cma0_s(24) <= u0_m0_wo0_cma0_y(24); + u0_m0_wo0_cma0_s(25) <= u0_m0_wo0_cma0_y(25); + u0_m0_wo0_cma0_s(26) <= u0_m0_wo0_cma0_y(26); + u0_m0_wo0_cma0_s(27) <= u0_m0_wo0_cma0_y(27); + u0_m0_wo0_cma0_s(28) <= u0_m0_wo0_cma0_y(28); + u0_m0_wo0_cma0_s(29) <= u0_m0_wo0_cma0_y(29); + u0_m0_wo0_cma0_s(30) <= u0_m0_wo0_cma0_y(30); + u0_m0_wo0_cma0_s(31) <= u0_m0_wo0_cma0_y(31); + END IF; + END IF; + END PROCESS; + u0_m0_wo0_cma0_delay : dspba_delay + GENERIC MAP ( width => 36, depth => 0, reset_kind => "ASYNC" ) + PORT MAP ( xin => STD_LOGIC_VECTOR(u0_m0_wo0_cma0_s(0)(35 downto 0)), xout => u0_m0_wo0_cma0_qq, clk => clk, aclr => areset ); + u0_m0_wo0_cma0_q <= STD_LOGIC_VECTOR(u0_m0_wo0_cma0_qq(35 downto 0)); + + -- u0_m0_wo0_mtree_add0_0(ADD,106)@12 + 1 + u0_m0_wo0_mtree_add0_0_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 36 => u0_m0_wo0_cma0_q(35)) & u0_m0_wo0_cma0_q)); + u0_m0_wo0_mtree_add0_0_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 34 => u0_m0_wo0_cma1_q(33)) & u0_m0_wo0_cma1_q)); + u0_m0_wo0_mtree_add0_0_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_mtree_add0_0_o <= (others => '0'); + ELSIF (clk'EVENT AND clk = '1') THEN + u0_m0_wo0_mtree_add0_0_o <= STD_LOGIC_VECTOR(SIGNED(u0_m0_wo0_mtree_add0_0_a) + SIGNED(u0_m0_wo0_mtree_add0_0_b)); + END IF; + END PROCESS; + u0_m0_wo0_mtree_add0_0_q <= u0_m0_wo0_mtree_add0_0_o(36 downto 0); + + -- GND(CONSTANT,0)@0 + GND_q <= "0"; + + -- d_u0_m0_wo0_compute_q_12(DELAY,114)@11 + 1 + d_u0_m0_wo0_compute_q_12 : dspba_delay + GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" ) + PORT MAP ( xin => d_u0_m0_wo0_compute_q_11_q, xout => d_u0_m0_wo0_compute_q_12_q, clk => clk, aclr => areset ); + + -- u0_m0_wo0_oseq_gated_reg(REG,107)@12 + 1 + u0_m0_wo0_oseq_gated_reg_clkproc: PROCESS (clk, areset) + BEGIN + IF (areset = '1') THEN + u0_m0_wo0_oseq_gated_reg_q <= "0"; + ELSIF (clk'EVENT AND clk = '1') THEN + u0_m0_wo0_oseq_gated_reg_q <= STD_LOGIC_VECTOR(d_u0_m0_wo0_compute_q_12_q); + END IF; + END PROCESS; + + -- out0_m0_wo0_lineup_select_delay_0(DELAY,109)@13 + out0_m0_wo0_lineup_select_delay_0_q <= STD_LOGIC_VECTOR(u0_m0_wo0_oseq_gated_reg_q); + + -- out0_m0_wo0_assign_id3(DELAY,111)@13 + out0_m0_wo0_assign_id3_q <= STD_LOGIC_VECTOR(out0_m0_wo0_lineup_select_delay_0_q); + + -- xOut(PORTOUT,112)@13 + 1 + xOut_v <= out0_m0_wo0_assign_id3_q; + xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q); + xOut_0 <= u0_m0_wo0_mtree_add0_0_q; + +END normal; diff --git a/ld3/dds_vhdl/fir_import_coef.txt b/ld3/dds_vhdl/fir_import_coef.txt new file mode 100644 index 0000000..cb3696d --- /dev/null +++ b/ld3/dds_vhdl/fir_import_coef.txt @@ -0,0 +1,3 @@ +# banks: 1 +# coeffs: 41 +-0.0073 , -0.0071 , -0.0059 , -0.0024 , 0.0040 , 0.0132 , 0.0231 , 0.0301 , 0.0302 , 0.0207 , 0.0015 , -0.0242 , -0.0498 , -0.0677 , -0.0712 , -0.0571 , -0.0269 , 0.0129 , 0.0525 , 0.0814 , 0.0920 , 0.0814 , 0.0525 , 0.0129 , -0.0269 , -0.0571 , -0.0712 , -0.0677 , -0.0498 , -0.0242 , 0.0015 , 0.0207 , 0.0302 , 0.0301 , 0.0231 , 0.0132 , 0.0040 , -0.0024 , -0.0059 , -0.0071 , -0.0073 \ No newline at end of file diff --git a/ld3/dds_vhdl/fir_sim.f b/ld3/dds_vhdl/fir_sim.f new file mode 100644 index 0000000..7210ba1 --- /dev/null +++ b/ld3/dds_vhdl/fir_sim.f @@ -0,0 +1,20 @@ +fir_sim/dspba_library_package.vhd +fir_sim/dspba_library.vhd +fir_sim/auk_dspip_math_pkg_hpfir.vhd +fir_sim/auk_dspip_lib_pkg_hpfir.vhd +fir_sim/auk_dspip_avalon_streaming_controller_hpfir.vhd +fir_sim/auk_dspip_avalon_streaming_sink_hpfir.vhd +fir_sim/auk_dspip_avalon_streaming_source_hpfir.vhd +fir_sim/auk_dspip_roundsat_hpfir.vhd +fir_sim/altera_avalon_sc_fifo.v +fir_sim/fir_rtl_core.vhd +fir_sim/fir_ast.vhd +fir_sim/fir.vhd +fir_sim/fir_nativelink.tcl +fir_sim/fir_msim.tcl +fir_sim/fir_tb.vhd +fir_sim/fir_mlab.m +fir_sim/fir_model.m +fir_sim/fir_coef_int.txt +fir_sim/fir_input.txt +fir_sim/fir_param.txt diff --git a/ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl b/ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..04dced2 --- /dev/null +++ b/ld3/dds_vhdl/fir_sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,319 @@ + +# (C) 2001-2020 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 19.1 670 win32 2020.06.09.18:16:15 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# fir +# +# Altera recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Altera simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR + + + + + + + + + + + +
+
+
+

HDL Code Generation Check Report for 'ld3_fixed_point2/IIF' +open model 'ld3_fixed_point2/IIF'
+Generated on 2020-06-09 21:58:09

+

HDL check for 'ld3_fixed_point2' complete with 1 errors, 2 warnings, and 1 messages.


+

The following table describes blocks for which errors, warnings or messages were reported.


+ + + + + + + + + + + + + + + + + +
Simulink Blocks and resources Level Description
+ld3_fixed_point2 +ErrorDelay balancing unsuccessful because Signal rate of value 0 found. +Offending Block:ld3_fixed_point2/IIF/.
+ld3_fixed_point2/IIF/a(2) +WarningUnable to insert required number of pipeline registers because the block, ld3_fixed_point2/IIF/a(2), is in a feedback path. Number of registers required: 2; number of registers inserted: 0.
+ld3_fixed_point2/IIF/a(3) +WarningUnable to insert required number of pipeline registers because the block, ld3_fixed_point2/IIF/a(3), is in a feedback path. Number of registers required: 2; number of registers inserted: 0.
+C:\Users\Imants\Desktop\sin_gen\iif_hdl\ld3_fixed_point2\highlightFeedbackLoop.m +MessageOne or more feedback loops in the model are inhibiting optimizations. To highlight these loops in your model, click the following MATLAB script: C:\Users\Imants\Desktop\sin_gen\iif_hdl\ld3_fixed_point2\highlightFeedbackLoop.m
+

+
+
+
+ +
© 1994-2020 The MathWorks, Inc.
+
+
+
+ + + + + diff --git a/ld3/iif_hdl/ld3_fixed_point2/clearhighlighting.m b/ld3/iif_hdl/ld3_fixed_point2/clearhighlighting.m new file mode 100644 index 0000000..2d326b9 --- /dev/null +++ b/ld3/iif_hdl/ld3_fixed_point2/clearhighlighting.m @@ -0,0 +1,2 @@ +SLStudio.Utils.RemoveHighlighting(get_param('ld3_fixed_point2', 'handle')); +SLStudio.Utils.RemoveHighlighting(get_param('gm_ld3_fixed_point2', 'handle')); diff --git a/ld3/iif_hdl/ld3_fixed_point2/gm_ld3_fixed_point2.slx b/ld3/iif_hdl/ld3_fixed_point2/gm_ld3_fixed_point2.slx new file mode 100644 index 0000000..785e3a5 Binary files /dev/null and b/ld3/iif_hdl/ld3_fixed_point2/gm_ld3_fixed_point2.slx differ diff --git a/ld3/iif_hdl/ld3_fixed_point2/hdlcodegenstatus.mat b/ld3/iif_hdl/ld3_fixed_point2/hdlcodegenstatus.mat new file mode 100644 index 0000000..0a760b9 Binary files /dev/null and b/ld3/iif_hdl/ld3_fixed_point2/hdlcodegenstatus.mat differ diff --git a/ld3/iif_hdl/ld3_fixed_point2/highlightFeedbackLoop.m b/ld3/iif_hdl/ld3_fixed_point2/highlightFeedbackLoop.m new file mode 100644 index 0000000..3d8ef52 --- /dev/null +++ b/ld3/iif_hdl/ld3_fixed_point2/highlightFeedbackLoop.m @@ -0,0 +1,38 @@ +open_system('ld3_fixed_point2'); +open_system('gm_ld3_fixed_point2'); +cs.HiliteType = 'user1'; +cs.ForegroundColor = 'black'; +cs.BackgroundColor = 'cyan'; +set_param(0, 'HiliteAncestorsData', cs); +hilite_system('gm_ld3_fixed_point2/IIF/Delay', 'user1'); +hilite_system('ld3_fixed_point2/IIF/Delay', 'user1'); +cs.HiliteType = 'user1'; +cs.ForegroundColor = 'black'; +cs.BackgroundColor = 'cyan'; +set_param(0, 'HiliteAncestorsData', cs); +hilite_system('gm_ld3_fixed_point2/IIF/Delay1', 'user1'); +hilite_system('ld3_fixed_point2/IIF/Delay1', 'user1'); +cs.HiliteType = 'user1'; +cs.ForegroundColor = 'black'; +cs.BackgroundColor = 'cyan'; +set_param(0, 'HiliteAncestorsData', cs); +hilite_system('gm_ld3_fixed_point2/IIF/Subtract1', 'user1'); +hilite_system('ld3_fixed_point2/IIF/Subtract1', 'user1'); +cs.HiliteType = 'user1'; +cs.ForegroundColor = 'black'; +cs.BackgroundColor = 'cyan'; +set_param(0, 'HiliteAncestorsData', cs); +hilite_system('gm_ld3_fixed_point2/IIF/Subtract2', 'user1'); +hilite_system('ld3_fixed_point2/IIF/Subtract2', 'user1'); +cs.HiliteType = 'user1'; +cs.ForegroundColor = 'black'; +cs.BackgroundColor = 'cyan'; +set_param(0, 'HiliteAncestorsData', cs); +hilite_system('gm_ld3_fixed_point2/IIF/a(2)', 'user1'); +hilite_system('ld3_fixed_point2/IIF/a(2)', 'user1'); +cs.HiliteType = 'user1'; +cs.ForegroundColor = 'black'; +cs.BackgroundColor = 'cyan'; +set_param(0, 'HiliteAncestorsData', cs); +hilite_system('gm_ld3_fixed_point2/IIF/a(3)', 'user1'); +hilite_system('ld3_fixed_point2/IIF/a(3)', 'user1'); diff --git a/ld3/ld3.m b/ld3/ld3.m index 05163e6..6556b24 100644 --- a/ld3/ld3.m +++ b/ld3/ld3.m @@ -41,10 +41,10 @@ ylabel('Magnitude (dB)') legend('Response FIR_1','Response FIR_2','f_1','f_2', '-20dB target', 'Location','East') title('Magnitude response') %% 3.IIR bandpass filtrs -[b,a] = iirpeak(Wn1,2*(Wn2-Wn1),-22); %Wo must satisfy 0.0 < Wo < 1.0, with 1.0 corresponding to pi radians/sample -[h3,w3] = freqz(b,a); -[b,a] = iirpeak(Wn2,2*(Wn2-Wn1),-19); -[h4,w4] = freqz(b,a); +[bb1,aa1] = iirpeak(Wn1,2*(Wn2-Wn1),-22); %Wo must satisfy 0.0 < Wo < 1.0, with 1.0 corresponding to pi radians/sample +[h3,w3] = freqz(bb1,aa1); +[bb2,aa2] = iirpeak(Wn2,2*(Wn2-Wn1),-19); +[h4,w4] = freqz(bb2,aa2); figure (2) plot (w3/pi,db(h3), ... w4/pi,db(h4),... diff --git a/ld3/ld3_fixed_point.slx b/ld3/ld3_fixed_point.slx new file mode 100644 index 0000000..74cec9b Binary files /dev/null and b/ld3/ld3_fixed_point.slx differ diff --git a/ld3/ld3_fixed_point2.slx b/ld3/ld3_fixed_point2.slx new file mode 100644 index 0000000..68c146f Binary files /dev/null and b/ld3/ld3_fixed_point2.slx differ diff --git a/ld3/ls3_floting_point.slx b/ld3/ld3_floting_point.slx similarity index 65% rename from ld3/ls3_floting_point.slx rename to ld3/ld3_floting_point.slx index 96b6dc8..34f08e9 100644 Binary files a/ld3/ls3_floting_point.slx and b/ld3/ld3_floting_point.slx differ diff --git a/ld3/lookuptable.vhd b/ld3/lookuptable.vhd new file mode 100644 index 0000000..f948a96 --- /dev/null +++ b/ld3/lookuptable.vhd @@ -0,0 +1,516 @@ +type rom_table is array ( 0 to 2**9 - 1) of std_logic_vector(16 - 1 downto 0); +constant signal_rom_table : rom_table := +( + 0 => x"0000", + 1 => x"00c9", + 2 => x"0192", + 3 => x"025b", + 4 => x"0324", + 5 => x"03ed", + 6 => x"04b5", + 7 => x"057e", + 8 => x"0646", + 9 => x"070e", + 10 => x"07d6", + 11 => x"089d", + 12 => x"0964", + 13 => x"0a2b", + 14 => x"0af1", + 15 => x"0bb7", + 16 => x"0c7c", + 17 => x"0d41", + 18 => x"0e06", + 19 => x"0eca", + 20 => x"0f8d", + 21 => x"1050", + 22 => x"1112", + 23 => x"11d3", + 24 => x"1294", + 25 => x"1354", + 26 => x"1413", + 27 => x"14d2", + 28 => x"1590", + 29 => x"164d", + 30 => x"1709", + 31 => x"17c4", + 32 => x"187e", + 33 => x"1937", + 34 => x"19f0", + 35 => x"1aa7", + 36 => x"1b5d", + 37 => x"1c12", + 38 => x"1cc7", + 39 => x"1d7a", + 40 => x"1e2b", + 41 => x"1edc", + 42 => x"1f8c", + 43 => x"203a", + 44 => x"20e7", + 45 => x"2193", + 46 => x"223e", + 47 => x"22e7", + 48 => x"238f", + 49 => x"2435", + 50 => x"24da", + 51 => x"257e", + 52 => x"2620", + 53 => x"26c1", + 54 => x"2760", + 55 => x"27fe", + 56 => x"289a", + 57 => x"2935", + 58 => x"29ce", + 59 => x"2a65", + 60 => x"2afb", + 61 => x"2b8f", + 62 => x"2c22", + 63 => x"2cb2", + 64 => x"2d41", + 65 => x"2dcf", + 66 => x"2e5a", + 67 => x"2ee4", + 68 => x"2f6c", + 69 => x"2ff2", + 70 => x"3076", + 71 => x"30f9", + 72 => x"3179", + 73 => x"31f8", + 74 => x"3274", + 75 => x"32ef", + 76 => x"3368", + 77 => x"33df", + 78 => x"3453", + 79 => x"34c6", + 80 => x"3537", + 81 => x"35a6", + 82 => x"3612", + 83 => x"367d", + 84 => x"36e5", + 85 => x"374b", + 86 => x"37b0", + 87 => x"3812", + 88 => x"3872", + 89 => x"38cf", + 90 => x"392b", + 91 => x"3984", + 92 => x"39db", + 93 => x"3a30", + 94 => x"3a83", + 95 => x"3ad3", + 96 => x"3b21", + 97 => x"3b6d", + 98 => x"3bb6", + 99 => x"3bfd", + 100 => x"3c42", + 101 => x"3c85", + 102 => x"3cc5", + 103 => x"3d03", + 104 => x"3d3f", + 105 => x"3d78", + 106 => x"3daf", + 107 => x"3de3", + 108 => x"3e15", + 109 => x"3e45", + 110 => x"3e72", + 111 => x"3e9d", + 112 => x"3ec5", + 113 => x"3eeb", + 114 => x"3f0f", + 115 => x"3f30", + 116 => x"3f4f", + 117 => x"3f6b", + 118 => x"3f85", + 119 => x"3f9c", + 120 => x"3fb1", + 121 => x"3fc4", + 122 => x"3fd4", + 123 => x"3fe1", + 124 => x"3fec", + 125 => x"3ff5", + 126 => x"3ffb", + 127 => x"3fff", + 128 => x"4000", + 129 => x"3fff", + 130 => x"3ffb", + 131 => x"3ff5", + 132 => x"3fec", + 133 => x"3fe1", + 134 => x"3fd4", + 135 => x"3fc4", + 136 => x"3fb1", + 137 => x"3f9c", + 138 => x"3f85", + 139 => x"3f6b", + 140 => x"3f4f", + 141 => x"3f30", + 142 => x"3f0f", + 143 => x"3eeb", + 144 => x"3ec5", + 145 => x"3e9d", + 146 => x"3e72", + 147 => x"3e45", + 148 => x"3e15", + 149 => x"3de3", + 150 => x"3daf", + 151 => x"3d78", + 152 => x"3d3f", + 153 => x"3d03", + 154 => x"3cc5", + 155 => x"3c85", + 156 => x"3c42", + 157 => x"3bfd", + 158 => x"3bb6", + 159 => x"3b6d", + 160 => x"3b21", + 161 => x"3ad3", + 162 => x"3a83", + 163 => x"3a30", + 164 => x"39db", + 165 => x"3984", + 166 => x"392b", + 167 => x"38cf", + 168 => x"3872", + 169 => x"3812", + 170 => x"37b0", + 171 => x"374b", + 172 => x"36e5", + 173 => x"367d", + 174 => x"3612", + 175 => x"35a6", + 176 => x"3537", + 177 => x"34c6", + 178 => x"3453", + 179 => x"33df", + 180 => x"3368", + 181 => x"32ef", + 182 => x"3274", + 183 => x"31f8", + 184 => x"3179", + 185 => x"30f9", + 186 => x"3076", + 187 => x"2ff2", + 188 => x"2f6c", + 189 => x"2ee4", + 190 => x"2e5a", + 191 => x"2dcf", + 192 => x"2d41", + 193 => x"2cb2", + 194 => x"2c22", + 195 => x"2b8f", + 196 => x"2afb", + 197 => x"2a65", + 198 => x"29ce", + 199 => x"2935", + 200 => x"289a", + 201 => x"27fe", + 202 => x"2760", + 203 => x"26c1", + 204 => x"2620", + 205 => x"257e", + 206 => x"24da", + 207 => x"2435", + 208 => x"238f", + 209 => x"22e7", + 210 => x"223e", + 211 => x"2193", + 212 => x"20e7", + 213 => x"203a", + 214 => x"1f8c", + 215 => x"1edc", + 216 => x"1e2b", + 217 => x"1d7a", + 218 => x"1cc7", + 219 => x"1c12", + 220 => x"1b5d", + 221 => x"1aa7", + 222 => x"19f0", + 223 => x"1937", + 224 => x"187e", + 225 => x"17c4", + 226 => x"1709", + 227 => x"164d", + 228 => x"1590", + 229 => x"14d2", + 230 => x"1413", + 231 => x"1354", + 232 => x"1294", + 233 => x"11d3", + 234 => x"1112", + 235 => x"1050", + 236 => x"0f8d", + 237 => x"0eca", + 238 => x"0e06", + 239 => x"0d41", + 240 => x"0c7c", + 241 => x"0bb7", + 242 => x"0af1", + 243 => x"0a2b", + 244 => x"0964", + 245 => x"089d", + 246 => x"07d6", + 247 => x"070e", + 248 => x"0646", + 249 => x"057e", + 250 => x"04b5", + 251 => x"03ed", + 252 => x"0324", + 253 => x"025b", + 254 => x"0192", + 255 => x"00c9", + 256 => x"0000", + 257 => x"ff37", + 258 => x"fe6e", + 259 => x"fda5", + 260 => x"fcdc", + 261 => x"fc13", + 262 => x"fb4b", + 263 => x"fa82", + 264 => x"f9ba", + 265 => x"f8f2", + 266 => x"f82b", + 267 => x"f763", + 268 => x"f69c", + 269 => x"f5d5", + 270 => x"f50f", + 271 => x"f449", + 272 => x"f384", + 273 => x"f2bf", + 274 => x"f1fa", + 275 => x"f136", + 276 => x"f073", + 277 => x"efb0", + 278 => x"eeee", + 279 => x"ee2d", + 280 => x"ed6c", + 281 => x"ecac", + 282 => x"ebed", + 283 => x"eb2e", + 284 => x"ea71", + 285 => x"e9b4", + 286 => x"e8f8", + 287 => x"e83c", + 288 => x"e782", + 289 => x"e6c9", + 290 => x"e611", + 291 => x"e559", + 292 => x"e4a3", + 293 => x"e3ee", + 294 => x"e33a", + 295 => x"e287", + 296 => x"e1d5", + 297 => x"e124", + 298 => x"e074", + 299 => x"dfc6", + 300 => x"df19", + 301 => x"de6d", + 302 => x"ddc3", + 303 => x"dd1a", + 304 => x"dc72", + 305 => x"dbcb", + 306 => x"db26", + 307 => x"da82", + 308 => x"d9e0", + 309 => x"d93f", + 310 => x"d8a0", + 311 => x"d802", + 312 => x"d766", + 313 => x"d6cc", + 314 => x"d633", + 315 => x"d59b", + 316 => x"d505", + 317 => x"d471", + 318 => x"d3df", + 319 => x"d34e", + 320 => x"d2bf", + 321 => x"d232", + 322 => x"d1a6", + 323 => x"d11c", + 324 => x"d094", + 325 => x"d00e", + 326 => x"cf8a", + 327 => x"cf08", + 328 => x"ce87", + 329 => x"ce09", + 330 => x"cd8c", + 331 => x"cd11", + 332 => x"cc98", + 333 => x"cc22", + 334 => x"cbad", + 335 => x"cb3a", + 336 => x"cac9", + 337 => x"ca5b", + 338 => x"c9ee", + 339 => x"c984", + 340 => x"c91b", + 341 => x"c8b5", + 342 => x"c851", + 343 => x"c7ef", + 344 => x"c78f", + 345 => x"c731", + 346 => x"c6d6", + 347 => x"c67c", + 348 => x"c625", + 349 => x"c5d0", + 350 => x"c57e", + 351 => x"c52d", + 352 => x"c4df", + 353 => x"c493", + 354 => x"c44a", + 355 => x"c403", + 356 => x"c3be", + 357 => x"c37b", + 358 => x"c33b", + 359 => x"c2fd", + 360 => x"c2c2", + 361 => x"c288", + 362 => x"c252", + 363 => x"c21d", + 364 => x"c1eb", + 365 => x"c1bb", + 366 => x"c18e", + 367 => x"c163", + 368 => x"c13b", + 369 => x"c115", + 370 => x"c0f1", + 371 => x"c0d0", + 372 => x"c0b1", + 373 => x"c095", + 374 => x"c07b", + 375 => x"c064", + 376 => x"c04f", + 377 => x"c03d", + 378 => x"c02d", + 379 => x"c01f", + 380 => x"c014", + 381 => x"c00b", + 382 => x"c005", + 383 => x"c001", + 384 => x"c000", + 385 => x"c001", + 386 => x"c005", + 387 => x"c00b", + 388 => x"c014", + 389 => x"c01f", + 390 => x"c02d", + 391 => x"c03d", + 392 => x"c04f", + 393 => x"c064", + 394 => x"c07b", + 395 => x"c095", + 396 => x"c0b1", + 397 => x"c0d0", + 398 => x"c0f1", + 399 => x"c115", + 400 => x"c13b", + 401 => x"c163", + 402 => x"c18e", + 403 => x"c1bb", + 404 => x"c1eb", + 405 => x"c21d", + 406 => x"c252", + 407 => x"c288", + 408 => x"c2c2", + 409 => x"c2fd", + 410 => x"c33b", + 411 => x"c37b", + 412 => x"c3be", + 413 => x"c403", + 414 => x"c44a", + 415 => x"c493", + 416 => x"c4df", + 417 => x"c52d", + 418 => x"c57e", + 419 => x"c5d0", + 420 => x"c625", + 421 => x"c67c", + 422 => x"c6d6", + 423 => x"c731", + 424 => x"c78f", + 425 => x"c7ef", + 426 => x"c851", + 427 => x"c8b5", + 428 => x"c91b", + 429 => x"c984", + 430 => x"c9ee", + 431 => x"ca5b", + 432 => x"cac9", + 433 => x"cb3a", + 434 => x"cbad", + 435 => x"cc22", + 436 => x"cc98", + 437 => x"cd11", + 438 => x"cd8c", + 439 => x"ce09", + 440 => x"ce87", + 441 => x"cf08", + 442 => x"cf8a", + 443 => x"d00e", + 444 => x"d094", + 445 => x"d11c", + 446 => x"d1a6", + 447 => x"d232", + 448 => x"d2bf", + 449 => x"d34e", + 450 => x"d3df", + 451 => x"d471", + 452 => x"d505", + 453 => x"d59b", + 454 => x"d633", + 455 => x"d6cc", + 456 => x"d766", + 457 => x"d802", + 458 => x"d8a0", + 459 => x"d93f", + 460 => x"d9e0", + 461 => x"da82", + 462 => x"db26", + 463 => x"dbcb", + 464 => x"dc72", + 465 => x"dd1a", + 466 => x"ddc3", + 467 => x"de6d", + 468 => x"df19", + 469 => x"dfc6", + 470 => x"e074", + 471 => x"e124", + 472 => x"e1d5", + 473 => x"e287", + 474 => x"e33a", + 475 => x"e3ee", + 476 => x"e4a3", + 477 => x"e559", + 478 => x"e611", + 479 => x"e6c9", + 480 => x"e782", + 481 => x"e83c", + 482 => x"e8f8", + 483 => x"e9b4", + 484 => x"ea71", + 485 => x"eb2e", + 486 => x"ebed", + 487 => x"ecac", + 488 => x"ed6c", + 489 => x"ee2d", + 490 => x"eeee", + 491 => x"efb0", + 492 => x"f073", + 493 => x"f136", + 494 => x"f1fa", + 495 => x"f2bf", + 496 => x"f384", + 497 => x"f449", + 498 => x"f50f", + 499 => x"f5d5", + 500 => x"f69c", + 501 => x"f763", + 502 => x"f82b", + 503 => x"f8f2", + 504 => x"f9ba", + 505 => x"fa82", + 506 => x"fb4b", + 507 => x"fc13", + 508 => x"fcdc", + 509 => x"fda5", + 510 => x"fe6e", + 511 => x"ff37", +); diff --git a/ld3/ls3_fixed_point.slx b/ld3/ls3_fixed_point.slx deleted file mode 100644 index e63dde6..0000000 Binary files a/ld3/ls3_fixed_point.slx and /dev/null differ diff --git a/ld3/table_gen.m b/ld3/table_gen.m index eb29cb5..a04bb84 100644 --- a/ld3/table_gen.m +++ b/ld3/table_gen.m @@ -29,42 +29,24 @@ hex_cos = []; for i=1:2^table_size a = sfi(sin_x(i),word_lenght,word_lenght-2); b = sfi(cos_x(i),word_lenght,word_lenght-2); - hex_sin = [hex_sin; a.bin]; - hex_cos = [hex_cos; b.bin]; + hex_sin = [hex_sin; a.hex]; + hex_cos = [hex_cos; b.hex]; end %hex_sin, %hex_cos, -fid = fopen('lookuptable.v', 'wt'); - fprintf(fid, 'module lookuptable #( parameter phase_width = %d, data_width = %d)(\n', table_size, word_lenght); - fprintf(fid, '\tinput [phase_width - 1 :0] phase,\n'); - fprintf(fid, '\toutput reg [data_width - 1 :0] sin,\n'); - fprintf(fid, '\toutput reg [data_width - 1 :0] cos);\n'); - -% fprintf(fid, 'reg [%d :0] sin = %d''h0; \n', word_lenght-1,word_lenght); - fprintf(fid, 'always@* begin\n'); - fprintf(fid, 'case (phase[phase_width - 1 : 0])\n'); +fid = fopen('lookuptable.vhd', 'wt'); + fprintf(fid, 'type rom_table is array ( 0 to 2**%d - 1) of std_logic_vector(%d - 1 downto 0);\n', table_size, word_lenght); + fprintf(fid, 'constant signal_rom_table : rom_table := \n'); + fprintf(fid, '(\n'); for i=1:length(hex_sin) - temp = hex_sin(i,1:word_lenght); - fprintf(fid, '\t%d''d%d : sin[data_width - 1 : 0] <= %d''b%s;\n',table_size, i-1 ,word_lenght, hex_sin(i,1:word_lenght) ); + temp = hex_sin(i,1:word_lenght/4); + fprintf(fid, '\t%d => x"%s",\n', i-1, hex_sin(i,1:word_lenght/4) ); end - fprintf(fid, '\tdefault : sin[data_width - 1 : 0] <= %d''b%s;\n ',word_lenght, hex_sin(1,1:word_lenght) ); - fprintf(fid, 'endcase\n'); - fprintf(fid, 'end\n'); - fprintf(fid, ' \n'); - fprintf(fid, 'always@* begin\n'); - fprintf(fid, 'case (phase[phase_width - 1 : 0])\n'); - -for i=1:length(hex_cos) - temp = hex_cos(i,1:word_lenght); - fprintf(fid, '\t%d''d%d : cos[data_width - 1 : 0] <= %d''b%s;\n',table_size, i-1 , word_lenght, hex_cos(i,1:word_lenght) ); -end - fprintf(fid, '\tdefault : cos[data_width - 1 : 0] <= %d''b%s;\n ',word_lenght, hex_cos(1,1:word_lenght) ); - fprintf(fid, 'endcase\n'); - fprintf(fid, 'end\n'); - fprintf(fid, 'endmodule'); + fprintf(fid, ');\n'); + disp('Text files write done');disp(' '); fclose(fid); \ No newline at end of file