130 lines
3.2 KiB
Verilog
130 lines
3.2 KiB
Verilog
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module PS2_Demo (
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// Inputs
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CLOCK_50,
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KEY,
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// Bidirectionals
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PS2_CLK,
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PS2_DAT,
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// Outputs
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HEX0,
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HEX1,
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HEX2,
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HEX3,
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HEX4,
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HEX5,
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HEX6,
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HEX7
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);
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/*****************************************************************************
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* Parameter Declarations *
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*****************************************************************************/
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/*****************************************************************************
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* Port Declarations *
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*****************************************************************************/
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// Inputs
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input CLOCK_50;
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input [3:0] KEY;
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// Bidirectionals
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inout PS2_CLK;
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inout PS2_DAT;
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// Outputs
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output [6:0] HEX0;
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output [6:0] HEX1;
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output [6:0] HEX2;
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output [6:0] HEX3;
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output [6:0] HEX4;
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output [6:0] HEX5;
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output [6:0] HEX6;
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output [6:0] HEX7;
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/*****************************************************************************
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* Internal Wires and Registers Declarations *
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*****************************************************************************/
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// Internal Wires
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wire [7:0] ps2_key_data;
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wire ps2_key_pressed;
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// Internal Registers
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reg [7:0] last_data_received;
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// State Machine Registers
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/*****************************************************************************
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* Finite State Machine(s) *
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*****************************************************************************/
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/*****************************************************************************
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* Sequential Logic *
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*****************************************************************************/
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always @(posedge CLOCK_50)
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begin
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if (KEY[0] == 1'b0)
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last_data_received <= 8'h00;
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else if (ps2_key_pressed == 1'b1)
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last_data_received <= ps2_key_data;
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end
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/*****************************************************************************
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* Combinational Logic *
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*****************************************************************************/
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assign HEX2 = 7'h7F;
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assign HEX3 = 7'h7F;
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assign HEX4 = 7'h7F;
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assign HEX5 = 7'h7F;
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assign HEX6 = 7'h7F;
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assign HEX7 = 7'h7F;
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/*****************************************************************************
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* Internal Modules *
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*****************************************************************************/
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PS2_Controller PS2 (
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// Inputs
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.CLOCK_50 (CLOCK_50),
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.reset (~KEY[0]),
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// Bidirectionals
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.PS2_CLK (PS2_CLK),
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.PS2_DAT (PS2_DAT),
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// Outputs
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.received_data (ps2_key_data),
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.received_data_en (ps2_key_pressed)
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);
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Hexadecimal_To_Seven_Segment Segment0 (
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// Inputs
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.hex_number (last_data_received[3:0]),
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// Bidirectional
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// Outputs
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.seven_seg_display (HEX0)
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);
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Hexadecimal_To_Seven_Segment Segment1 (
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// Inputs
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.hex_number (last_data_received[7:4]),
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// Bidirectional
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// Outputs
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.seven_seg_display (HEX1)
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);
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endmodule
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