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This commit is contained in:
Imants Pulkstenis
2019-07-18 22:05:52 +03:00
parent b3d2c42acd
commit 3432b15530
14 changed files with 2666 additions and 3 deletions
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PS2_Demo/Altera_UP_PS2_Command_Out.v
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/*****************************************************************************
* *
* Module: Altera_UP_PS2_Command_Out *
* Description: *
* This module sends commands out to the PS2 core. *
* *
*****************************************************************************/
module Altera_UP_PS2_Command_Out (
// Inputs
clk,
reset,
the_command,
send_command,
ps2_clk_posedge,
ps2_clk_negedge,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
command_was_sent,
error_communication_timed_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for initiating Host-to-Device communication
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_101US = 5050;
parameter NUMBER_OF_BITS_FOR_101US = 13;
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001;
//parameter CLOCK_CYCLES_FOR_101US = 50;
//parameter NUMBER_OF_BITS_FOR_101US = 6;
//parameter COUNTER_INCREMENT_FOR_101US = 6'h01;
// Timing info for start of transmission error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 750000;
parameter NUMBER_OF_BITS_FOR_15MS = 20;
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001;
// Timing info for sending data error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 100000;
parameter NUMBER_OF_BITS_FOR_2MS = 17;
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [7:0] the_command;
input send_command;
input ps2_clk_posedge;
input ps2_clk_negedge;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output reg command_was_sent;
output reg error_communication_timed_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [3:0] cur_bit;
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
// State Machine Registers
reg [2:0] ns_ps2_transmitter;
reg [2:0] s_ps2_transmitter;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_transmitter <= PS2_STATE_0_IDLE;
else
s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*)
begin
// Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1)
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
ps2_command <= 9'h000;
else if (s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if (s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if (s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else
begin
if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if (transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
cur_bit <= 4'h0;
else if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if (s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_was_sent <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if (send_command == 1'b0)
command_was_sent <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
error_communication_timed_out <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if (send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign PS2_CLK =
(s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ?
1'b0 :
1'bz;
assign PS2_DAT =
(s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 :
1'bz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
PS2_Demo/Altera_UP_PS2_Data_In.v
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/*****************************************************************************
* *
* Module: Altera_UP_PS2_Data_In *
* Description: *
* This module accepts incoming data from a PS2 core. *
* *
*****************************************************************************/
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
PS2_Demo/Hexadecimal_To_Seven_Segment.v
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/******************************************************************************
* *
* Module: Hexadecimal_To_Seven_Segment *
* Description: *
* This module converts hexadecimal numbers for seven segment displays. *
* *
******************************************************************************/
module Hexadecimal_To_Seven_Segment (
// Inputs
hex_number,
// Bidirectional
// Outputs
seven_seg_display
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [3:0] hex_number;
// Bidirectional
// Outputs
output [6:0] seven_seg_display;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign seven_seg_display =
({7{(hex_number == 4'h0)}} & 7'b1000000) |
({7{(hex_number == 4'h1)}} & 7'b1111001) |
({7{(hex_number == 4'h2)}} & 7'b0100100) |
({7{(hex_number == 4'h3)}} & 7'b0110000) |
({7{(hex_number == 4'h4)}} & 7'b0011001) |
({7{(hex_number == 4'h5)}} & 7'b0010010) |
({7{(hex_number == 4'h6)}} & 7'b0000010) |
({7{(hex_number == 4'h7)}} & 7'b1111000) |
({7{(hex_number == 4'h8)}} & 7'b0000000) |
({7{(hex_number == 4'h9)}} & 7'b0010000) |
({7{(hex_number == 4'hA)}} & 7'b0001000) |
({7{(hex_number == 4'hB)}} & 7'b0000011) |
({7{(hex_number == 4'hC)}} & 7'b1000110) |
({7{(hex_number == 4'hD)}} & 7'b0100001) |
({7{(hex_number == 4'hE)}} & 7'b0000110) |
({7{(hex_number == 4'hF)}} & 7'b0001110);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
PS2_Demo/PS2_Controller.v
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/*****************************************************************************
* *
* Module: Altera_UP_PS2 *
* Description: *
* This module communicates with the PS2 core. *
* *
*****************************************************************************/
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input [7:0] the_command;
input send_command;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output command_was_sent;
output error_communication_timed_out;
output [7:0] received_data;
output received_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
if(INITIALIZE_MOUSE) begin
assign the_command_w = init_done ? the_command : 8'hf4;
assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
assign command_was_sent = init_done ? command_was_sent_w : 0;
assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
reg init_done;
always @(posedge CLOCK_50)
if(reset) init_done <= 0;
else if(command_was_sent_w) init_done <= 1;
end else begin
assign the_command_w = the_command;
assign send_command_w = send_command;
assign command_was_sent = command_was_sent_w;
assign error_communication_timed_out = error_communication_timed_out_w;
end
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire ps2_clk_posedge;
wire ps2_clk_negedge;
wire start_receiving_data;
wire wait_for_incoming_data;
// Internal Registers
reg [7:0] idle_counter;
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
// State Machine Registers
reg [2:0] ns_ps2_transceiver;
reg [2:0] s_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
s_ps2_transceiver <= PS2_STATE_0_IDLE;
else
s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
// Defaults
ns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if ((idle_counter == 8'hFF) &&
(send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else
ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if ((command_was_sent == 1'b1) ||
(error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if (received_data_en == 1'b1)
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else
begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= PS2_CLK;
ps2_data_reg <= PS2_DAT;
end
end
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
idle_counter <= 6'h00;
else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
(idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data =
(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
// Bidirectionals
// Outputs
.received_data (received_data),
.received_data_en (received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.the_command (the_command_w),
.send_command (send_command_w),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.command_was_sent (command_was_sent_w),
.error_communication_timed_out (error_communication_timed_out_w)
);
endmodule
PS2_Demo/PS2_Demo.pin
+736
View File
@@ -0,0 +1,736 @@
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
CHIP "PS2_Demo" ASSIGNED TO AN: EP2C35F672C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A2 : gnd : : : :
VCCIO3 : A3 : power : : 3.3V : 3 :
GND* : A4 : : : : 3 :
GND* : A5 : : : : 3 :
GND* : A6 : : : : 3 :
GND* : A7 : : : : 3 :
GND* : A8 : : : : 3 :
GND* : A9 : : : : 3 :
GND* : A10 : : : : 3 :
VCCIO3 : A11 : power : : 3.3V : 3 :
GND : A12 : gnd : : : :
GND+ : A13 : : : : 4 :
GND* : A14 : : : : 4 :
GND : A15 : gnd : : : :
VCCIO4 : A16 : power : : 3.3V : 4 :
GND* : A17 : : : : 4 :
GND* : A18 : : : : 4 :
GND* : A19 : : : : 4 :
GND* : A20 : : : : 4 :
GND* : A21 : : : : 4 :
GND* : A22 : : : : 4 :
GND* : A23 : : : : 4 :
VCCIO4 : A24 : power : : 3.3V : 4 :
GND : A25 : gnd : : : :
GND* : AA1 : : : : 1 :
GND* : AA2 : : : : 1 :
GND* : AA3 : : : : 1 :
GND* : AA4 : : : : 1 :
GND* : AA5 : : : : 1 :
GND* : AA6 : : : : 1 :
GND* : AA7 : : : : 1 :
VCCA_PLL1 : AA8 : power : : 1.2V : :
GND* : AA9 : : : : 8 :
GND* : AA10 : : : : 8 :
GND* : AA11 : : : : 8 :
GND* : AA12 : : : : 8 :
GND* : AA13 : : : : 7 :
GND* : AA14 : : : : 7 :
GND* : AA15 : : : : 7 :
GND* : AA16 : : : : 7 :
GND* : AA17 : : : : 7 :
GND* : AA18 : : : : 7 :
VCCA_PLL4 : AA19 : power : : 1.2V : :
GND* : AA20 : : : : 7 :
GND_PLL4 : AA21 : gnd : : : :
VCCIO6 : AA22 : power : : 3.3V : 6 :
HEX1[5] : AA23 : output : 3.3-V LVTTL : : 6 : Y
HEX1[4] : AA24 : output : 3.3-V LVTTL : : 6 : Y
HEX3[1] : AA25 : output : 3.3-V LVTTL : : 6 : Y
HEX3[2] : AA26 : output : 3.3-V LVTTL : : 6 : Y
GND* : AB1 : : : : 1 :
GND* : AB2 : : : : 1 :
GND* : AB3 : : : : 1 :
GND* : AB4 : : : : 1 :
VCCIO1 : AB5 : power : : 3.3V : 1 :
VCCIO8 : AB6 : power : : 3.3V : 8 :
GND : AB7 : gnd : : : :
GND* : AB8 : : : : 8 :
VCCIO8 : AB9 : power : : 3.3V : 8 :
GND* : AB10 : : : : 8 :
GND : AB11 : gnd : : : :
HEX0[1] : AB12 : output : 3.3-V LVTTL : : 8 : Y
VCCIO8 : AB13 : power : : 3.3V : 8 :
VCCIO7 : AB14 : power : : 3.3V : 7 :
GND* : AB15 : : : : 7 :
GND : AB16 : gnd : : : :
VCCIO7 : AB17 : power : : 3.3V : 7 :
GND* : AB18 : : : : 7 :
GND : AB19 : gnd : : : :
GND* : AB20 : : : : 7 :
GND* : AB21 : : : : 7 :
VCCIO7 : AB22 : power : : 3.3V : 7 :
HEX2[0] : AB23 : output : 3.3-V LVTTL : : 6 : Y
HEX1[6] : AB24 : output : 3.3-V LVTTL : : 6 : Y
HEX2[5] : AB25 : output : 3.3-V LVTTL : : 6 : Y
HEX2[4] : AB26 : output : 3.3-V LVTTL : : 6 : Y
GND* : AC1 : : : : 1 :
GND* : AC2 : : : : 1 :
GND* : AC3 : : : : 1 :
GND : AC4 : gnd : : : :
GND* : AC5 : : : : 8 :
GND* : AC6 : : : : 8 :
GND* : AC7 : : : : 8 :
GND* : AC8 : : : : 8 :
GND* : AC9 : : : : 8 :
GND* : AC10 : : : : 8 :
GND* : AC11 : : : : 8 :
HEX0[2] : AC12 : output : 3.3-V LVTTL : : 8 : Y
GND+ : AC13 : : : : 8 :
GND* : AC14 : : : : 7 :
GND* : AC15 : : : : 7 :
GND* : AC16 : : : : 7 :
GND* : AC17 : : : : 7 :
GND* : AC18 : : : : 7 :
GND* : AC19 : : : : 7 :
GND* : AC20 : : : : 7 :
GND* : AC21 : : : : 7 :
GND* : AC22 : : : : 7 :
GND* : AC23 : : : : 6 :
NC : AC24 : : : : :
HEX2[2] : AC25 : output : 3.3-V LVTTL : : 6 : Y
HEX2[3] : AC26 : output : 3.3-V LVTTL : : 6 : Y
VCCIO1 : AD1 : power : : 3.3V : 1 :
GND* : AD2 : : : : 1 :
GND* : AD3 : : : : 1 :
GND* : AD4 : : : : 8 :
GND* : AD5 : : : : 8 :
GND* : AD6 : : : : 8 :
GND* : AD7 : : : : 8 :
GND* : AD8 : : : : 8 :
GND : AD9 : gnd : : : :
GND* : AD10 : : : : 8 :
HEX0[3] : AD11 : output : 3.3-V LVTTL : : 8 : Y
GND* : AD12 : : : : 8 :
GND+ : AD13 : : : : 8 :
GND : AD14 : gnd : : : :
GND* : AD15 : : : : 7 :
GND* : AD16 : : : : 7 :
GND* : AD17 : : : : 7 :
GND : AD18 : gnd : : : :
GND* : AD19 : : : : 7 :
VCCIO7 : AD20 : power : : 3.3V : 7 :
GND* : AD21 : : : : 7 :
GND* : AD22 : : : : 7 :
GND* : AD23 : : : : 7 :
GND* : AD24 : : : : 6 :
GND* : AD25 : : : : 6 :
VCCIO6 : AD26 : power : : 3.3V : 6 :
GND : AE1 : gnd : : : :
GND* : AE2 : : : : 1 :
GND* : AE3 : : : : 1 :
GND* : AE4 : : : : 8 :
GND* : AE5 : : : : 8 :
GND* : AE6 : : : : 8 :
GND* : AE7 : : : : 8 :
GND* : AE8 : : : : 8 :
GND* : AE9 : : : : 8 :
GND* : AE10 : : : : 8 :
HEX0[4] : AE11 : output : 3.3-V LVTTL : : 8 : Y
GND* : AE12 : : : : 8 :
GND* : AE13 : : : : 8 :
GND+ : AE14 : : : : 7 :
GND* : AE15 : : : : 7 :
GND* : AE16 : : : : 7 :
GND* : AE17 : : : : 7 :
GND* : AE18 : : : : 7 :
GND* : AE19 : : : : 7 :
GND* : AE20 : : : : 7 :
GND* : AE21 : : : : 7 :
GND* : AE22 : : : : 7 :
GND* : AE23 : : : : 7 :
~LVDS150p/nCEO~ : AE24 : output : 3.3-V LVTTL : : 6 : N
GND* : AE25 : : : : 6 :
GND : AE26 : gnd : : : :
GND : AF2 : gnd : : : :
VCCIO8 : AF3 : power : : 3.3V : 8 :
GND* : AF4 : : : : 8 :
GND* : AF5 : : : : 8 :
GND* : AF6 : : : : 8 :
GND* : AF7 : : : : 8 :
GND* : AF8 : : : : 8 :
GND* : AF9 : : : : 8 :
HEX0[0] : AF10 : output : 3.3-V LVTTL : : 8 : Y
VCCIO8 : AF11 : power : : 3.3V : 8 :
GND : AF12 : gnd : : : :
GND* : AF13 : : : : 8 :
GND+ : AF14 : : : : 7 :
GND : AF15 : gnd : : : :
VCCIO7 : AF16 : power : : 3.3V : 7 :
GND* : AF17 : : : : 7 :
GND* : AF18 : : : : 7 :
GND* : AF19 : : : : 7 :
GND* : AF20 : : : : 7 :
GND* : AF21 : : : : 7 :
GND* : AF22 : : : : 7 :
GND* : AF23 : : : : 7 :
VCCIO7 : AF24 : power : : 3.3V : 7 :
GND : AF25 : gnd : : : :
GND : B1 : gnd : : : :
GND* : B2 : : : : 2 :
GND* : B3 : : : : 2 :
GND* : B4 : : : : 3 :
GND* : B5 : : : : 3 :
GND* : B6 : : : : 3 :
GND* : B7 : : : : 3 :
GND* : B8 : : : : 3 :
GND* : B9 : : : : 3 :
GND* : B10 : : : : 3 :
GND* : B11 : : : : 3 :
GND* : B12 : : : : 3 :
GND+ : B13 : : : : 4 :
GND* : B14 : : : : 4 :
GND* : B15 : : : : 4 :
GND* : B16 : : : : 4 :
GND* : B17 : : : : 4 :
GND* : B18 : : : : 4 :
GND* : B19 : : : : 4 :
GND* : B20 : : : : 4 :
GND* : B21 : : : : 4 :
GND* : B22 : : : : 4 :
GND* : B23 : : : : 4 :
GND* : B24 : : : : 5 :
GND* : B25 : : : : 5 :
GND : B26 : gnd : : : :
VCCIO2 : C1 : power : : 3.3V : 2 :
GND* : C2 : : : : 2 :
GND* : C3 : : : : 2 :
GND* : C4 : : : : 3 :
GND* : C5 : : : : 3 :
GND* : C6 : : : : 3 :
GND* : C7 : : : : 3 :
GND* : C8 : : : : 3 :
GND* : C9 : : : : 3 :
GND* : C10 : : : : 3 :
GND* : C11 : : : : 3 :
GND* : C12 : : : : 3 :
GND+ : C13 : : : : 3 :
GND : C14 : gnd : : : :
GND* : C15 : : : : 4 :
GND* : C16 : : : : 4 :
GND* : C17 : : : : 4 :
GND : C18 : gnd : : : :
GND* : C19 : : : : 4 :
VCCIO4 : C20 : power : : 3.3V : 4 :
GND* : C21 : : : : 4 :
GND* : C22 : : : : 4 :
GND* : C23 : : : : 4 :
PS2_DAT : C24 : bidir : 3.3-V LVTTL : : 5 : Y
GND* : C25 : : : : 5 :
VCCIO5 : C26 : power : : 3.3V : 5 :
GND* : D1 : : : : 2 :
GND* : D2 : : : : 2 :
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : input : 3.3-V LVTTL : : 2 : N
GND : D4 : gnd : : : :
GND* : D5 : : : : 3 :
GND* : D6 : : : : 3 :
GND* : D7 : : : : 3 :
GND* : D8 : : : : 3 :
GND* : D9 : : : : 3 :
GND* : D10 : : : : 3 :
GND* : D11 : : : : 3 :
GND* : D12 : : : : 3 :
GND+ : D13 : : : : 3 :
GND* : D14 : : : : 4 :
GND* : D15 : : : : 4 :
GND* : D16 : : : : 4 :
GND* : D17 : : : : 4 :
GND* : D18 : : : : 4 :
GND* : D19 : : : : 4 :
GND* : D20 : : : : 4 :
GND* : D21 : : : : 4 :
VCCIO4 : D22 : power : : 3.3V : 4 :
GND* : D23 : : : : 5 :
GND : D24 : gnd : : : :
GND* : D25 : : : : 5 :
PS2_CLK : D26 : bidir : 3.3-V LVTTL : : 5 : Y
GND* : E1 : : : : 2 :
GND* : E2 : : : : 2 :
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : input : 3.3-V LVTTL : : 2 : N
GND_PLL3 : E4 : gnd : : : :
GND* : E5 : : : : 2 :
VCCIO3 : E6 : power : : 3.3V : 3 :
GND : E7 : gnd : : : :
GND* : E8 : : : : 3 :
VCCIO3 : E9 : power : : 3.3V : 3 :
GND* : E10 : : : : 3 :
GND : E11 : gnd : : : :
GND* : E12 : : : : 3 :
VCCIO3 : E13 : power : : 3.3V : 3 :
VCCIO4 : E14 : power : : 3.3V : 4 :
GND* : E15 : : : : 4 :
GND : E16 : gnd : : : :
VCCIO4 : E17 : power : : 3.3V : 4 :
GND* : E18 : : : : 4 :
GND : E19 : gnd : : : :
GND* : E20 : : : : 4 :
GND_PLL2 : E21 : gnd : : : :
GND* : E22 : : : : 5 :
GND* : E23 : : : : 5 :
GND* : E24 : : : : 5 :
GND* : E25 : : : : 5 :
GND* : E26 : : : : 5 :
GND* : F1 : : : : 2 :
GND* : F2 : : : : 2 :
GND* : F3 : : : : 2 :
GND* : F4 : : : : 2 :
VCCIO2 : F5 : power : : 3.3V : 2 :
GND* : F6 : : : : 2 :
GND* : F7 : : : : 2 :
GNDA_PLL3 : F8 : gnd : : : :
GND* : F9 : : : : 3 :
GND* : F10 : : : : 3 :
GND* : F11 : : : : 3 :
GND* : F12 : : : : 3 :
GND* : F13 : : : : 4 :
GND* : F14 : : : : 4 :
GND* : F15 : : : : 4 :
GND* : F16 : : : : 4 :
GND* : F17 : : : : 4 :
GND* : F18 : : : : 4 :
GNDA_PLL2 : F19 : gnd : : : :
GND* : F20 : : : : 5 :
GND* : F21 : : : : 5 :
VCCIO5 : F22 : power : : 3.3V : 5 :
GND* : F23 : : : : 5 :
GND* : F24 : : : : 5 :
GND* : F25 : : : : 5 :
GND* : F26 : : : : 5 :
GND* : G1 : : : : 2 :
GND* : G2 : : : : 2 :
GND* : G3 : : : : 2 :
GND* : G4 : : : : 2 :
GND* : G5 : : : : 2 :
GND* : G6 : : : : 2 :
GND_PLL3 : G7 : gnd : : : :
VCCA_PLL3 : G8 : power : : 1.2V : :
GND* : G9 : : : : 3 :
GND* : G10 : : : : 3 :
GND* : G11 : : : : 3 :
GND* : G12 : : : : 3 :
GND* : G13 : : : : 4 :
GND* : G14 : : : : 4 :
GND* : G15 : : : : 4 :
GND* : G16 : : : : 4 :
GND* : G17 : : : : 4 :
GND* : G18 : : : : 4 :
VCCA_PLL2 : G19 : power : : 1.2V : :
GND_PLL2 : G20 : gnd : : : :
GND* : G21 : : : : 5 :
GND* : G22 : : : : 5 :
GND* : G23 : : : : 5 :
GND* : G24 : : : : 5 :
GND* : G25 : : : : 5 :
KEY[0] : G26 : input : 3.3-V LVTTL : : 5 : Y
GND* : H1 : : : : 2 :
GND* : H2 : : : : 2 :
GND* : H3 : : : : 2 :
GND* : H4 : : : : 2 :
GND : H5 : gnd : : : :
GND* : H6 : : : : 2 :
VCCD_PLL3 : H7 : power : : 1.2V : :
GND* : H8 : : : : 3 :
VCCIO3 : H9 : power : : 3.3V : 3 :
GND* : H10 : : : : 3 :
GND* : H11 : : : : 3 :
GND* : H12 : : : : 3 :
GND : H13 : gnd : : : :
GND : H14 : gnd : : : :
GND* : H15 : : : : 4 :
GND* : H16 : : : : 4 :
GND* : H17 : : : : 4 :
VCCIO4 : H18 : power : : 3.3V : 4 :
GND* : H19 : : : : 5 :
VCCD_PLL2 : H20 : power : : 1.2V : :
GND* : H21 : : : : 5 :
GND : H22 : gnd : : : :
GND* : H23 : : : : 5 :
GND* : H24 : : : : 5 :
GND* : H25 : : : : 5 :
GND* : H26 : : : : 5 :
GND* : J1 : : : : 2 :
GND* : J2 : : : : 2 :
GND* : J3 : : : : 2 :
GND* : J4 : : : : 2 :
GND* : J5 : : : : 2 :
GND* : J6 : : : : 2 :
GND* : J7 : : : : 2 :
GND* : J8 : : : : 2 :
GND* : J9 : : : : 3 :
GND* : J10 : : : : 3 :
GND* : J11 : : : : 3 :
VCCIO3 : J12 : power : : 3.3V : 3 :
GND* : J13 : : : : 3 :
GND* : J14 : : : : 3 :
VCCIO4 : J15 : power : : 3.3V : 4 :
GND* : J16 : : : : 4 :
GND* : J17 : : : : 4 :
GND* : J18 : : : : 4 :
VCCIO5 : J19 : power : : 3.3V : 5 :
GND* : J20 : : : : 5 :
GND* : J21 : : : : 5 :
GND* : J22 : : : : 5 :
GND* : J23 : : : : 5 :
GND* : J24 : : : : 5 :
GND* : J25 : : : : 5 :
GND* : J26 : : : : 5 :
GND* : K1 : : : : 2 :
GND* : K2 : : : : 2 :
GND* : K3 : : : : 2 :
GND* : K4 : : : : 2 :
GND* : K5 : : : : 2 :
GND* : K6 : : : : 2 :
GND* : K7 : : : : 2 :
GND* : K8 : : : : 2 :
GND* : K9 : : : : 3 :
VCCINT : K10 : power : : 1.2V : :
VCCINT : K11 : power : : 1.2V : :
VCCINT : K12 : power : : 1.2V : :
VCCINT : K13 : power : : 1.2V : :
VCCINT : K14 : power : : 1.2V : :
VCCINT : K15 : power : : 1.2V : :
GND* : K16 : : : : 4 :
GND* : K17 : : : : 4 :
GND* : K18 : : : : 5 :
GND* : K19 : : : : 5 :
GND : K20 : gnd : : : :
GND* : K21 : : : : 5 :
GND* : K22 : : : : 5 :
GND* : K23 : : : : 5 :
GND* : K24 : : : : 5 :
GND* : K25 : : : : 5 :
GND* : K26 : : : : 5 :
VCCIO2 : L1 : power : : 3.3V : 2 :
HEX7[1] : L2 : output : 3.3-V LVTTL : : 2 : Y
HEX7[0] : L3 : output : 3.3-V LVTTL : : 2 : Y
GND* : L4 : : : : 2 :
GND : L5 : gnd : : : :
HEX7[3] : L6 : output : 3.3-V LVTTL : : 2 : Y
HEX7[4] : L7 : output : 3.3-V LVTTL : : 2 : Y
TMS : L8 : input : : : 2 :
HEX7[2] : L9 : output : 3.3-V LVTTL : : 2 : Y
GND* : L10 : : : : 2 :
VCCINT : L11 : power : : 1.2V : :
GND : L12 : gnd : : : :
GND : L13 : gnd : : : :
GND : L14 : gnd : : : :
GND : L15 : gnd : : : :
VCCINT : L16 : power : : 1.2V : :
VCCINT : L17 : power : : 1.2V : :
VCCINT : L18 : power : : 1.2V : :
GND* : L19 : : : : 5 :
GND* : L20 : : : : 5 :
GND* : L21 : : : : 5 :
GND : L22 : gnd : : : :
GND* : L23 : : : : 5 :
GND* : L24 : : : : 5 :
GND* : L25 : : : : 5 :
VCCIO5 : L26 : power : : 3.3V : 5 :
GND : M1 : gnd : : : :
HEX6[3] : M2 : output : 3.3-V LVTTL : : 2 : Y
HEX6[4] : M3 : output : 3.3-V LVTTL : : 2 : Y
HEX6[6] : M4 : output : 3.3-V LVTTL : : 2 : Y
HEX6[5] : M5 : output : 3.3-V LVTTL : : 2 : Y
TCK : M6 : input : : : 2 :
TDO : M7 : output : : : 2 :
TDI : M8 : input : : : 2 :
VCCIO2 : M9 : power : : 3.3V : 2 :
VCCINT : M10 : power : : 1.2V : :
VCCINT : M11 : power : : 1.2V : :
GND : M12 : gnd : : : :
GND : M13 : gnd : : : :
GND : M14 : gnd : : : :
GND : M15 : gnd : : : :
VCCINT : M16 : power : : 1.2V : :
VCCINT : M17 : power : : 1.2V : :
VCCIO5 : M18 : power : : 3.3V : 5 :
GND* : M19 : : : : 5 :
GND* : M20 : : : : 5 :
GND* : M21 : : : : 5 :
GND* : M22 : : : : 5 :
GND* : M23 : : : : 5 :
GND* : M24 : : : : 5 :
GND* : M25 : : : : 5 :
GND : M26 : gnd : : : :
GND+ : N1 : : : : 2 :
CLOCK_50 : N2 : input : 3.3-V LVTTL : : 2 : Y
DATA0 : N3 : input : : : 2 :
nCE : N4 : : : : 2 :
VCCIO2 : N5 : power : : 3.3V : 2 :
DCLK : N6 : : : : 2 :
nCONFIG : N7 : : : : 2 :
GND : N8 : gnd : : : :
HEX7[6] : N9 : output : 3.3-V LVTTL : : 2 : Y
VCCINT : N10 : power : : 1.2V : :
GND : N11 : gnd : : : :
GND : N12 : gnd : : : :
GND : N13 : gnd : : : :
GND : N14 : gnd : : : :
GND : N15 : gnd : : : :
GND : N16 : gnd : : : :
VCCINT : N17 : power : : 1.2V : :
GND* : N18 : : : : 5 :
GND : N19 : gnd : : : :
GND* : N20 : : : : 5 :
NC : N21 : : : : :
VCCIO5 : N22 : power : : 3.3V : 5 :
KEY[1] : N23 : input : 3.3-V LVTTL : : 5 : Y
GND* : N24 : : : : 5 :
GND+ : N25 : : : : 5 :
GND+ : N26 : : : : 5 :
GND+ : P1 : : : : 1 :
GND+ : P2 : : : : 1 :
HEX6[2] : P3 : output : 3.3-V LVTTL : : 1 : Y
HEX6[1] : P4 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : P5 : power : : 3.3V : 1 :
HEX5[1] : P6 : output : 3.3-V LVTTL : : 1 : Y
HEX5[2] : P7 : output : 3.3-V LVTTL : : 1 : Y
GND : P8 : gnd : : : :
HEX7[5] : P9 : output : 3.3-V LVTTL : : 2 : Y
VCCINT : P10 : power : : 1.2V : :
GND : P11 : gnd : : : :
GND : P12 : gnd : : : :
GND : P13 : gnd : : : :
GND : P14 : gnd : : : :
GND : P15 : gnd : : : :
GND : P16 : gnd : : : :
GND* : P17 : : : : 6 :
GND* : P18 : : : : 5 :
GND : P19 : gnd : : : :
MSEL0 : P20 : : : : 6 :
MSEL1 : P21 : : : : 6 :
VCCIO6 : P22 : power : : 3.3V : 6 :
KEY[2] : P23 : input : 3.3-V LVTTL : : 6 : Y
GND* : P24 : : : : 6 :
GND+ : P25 : : : : 6 :
GND+ : P26 : : : : 6 :
GND : R1 : gnd : : : :
HEX6[0] : R2 : output : 3.3-V LVTTL : : 1 : Y
HEX5[6] : R3 : output : 3.3-V LVTTL : : 1 : Y
HEX5[5] : R4 : output : 3.3-V LVTTL : : 1 : Y
HEX5[4] : R5 : output : 3.3-V LVTTL : : 1 : Y
HEX4[5] : R6 : output : 3.3-V LVTTL : : 1 : Y
HEX4[4] : R7 : output : 3.3-V LVTTL : : 1 : Y
GND* : R8 : : : : 1 :
VCCIO1 : R9 : power : : 3.3V : 1 :
VCCINT : R10 : power : : 1.2V : :
VCCINT : R11 : power : : 1.2V : :
GND : R12 : gnd : : : :
GND : R13 : gnd : : : :
GND : R14 : gnd : : : :
GND : R15 : gnd : : : :
VCCINT : R16 : power : : 1.2V : :
GND* : R17 : : : : 6 :
VCCIO6 : R18 : power : : 3.3V : 6 :
GND* : R19 : : : : 6 :
GND* : R20 : : : : 6 :
GND : R21 : gnd : : : :
nSTATUS : R22 : : : : 6 :
CONF_DONE : R23 : : : : 6 :
GND* : R24 : : : : 6 :
GND* : R25 : : : : 6 :
GND : R26 : gnd : : : :
VCCIO1 : T1 : power : : 3.3V : 1 :
HEX5[0] : T2 : output : 3.3-V LVTTL : : 1 : Y
HEX4[6] : T3 : output : 3.3-V LVTTL : : 1 : Y
HEX4[3] : T4 : output : 3.3-V LVTTL : : 1 : Y
GND : T5 : gnd : : : :
GND* : T6 : : : : 1 :
GND* : T7 : : : : 1 :
GND* : T8 : : : : 1 :
HEX5[3] : T9 : output : 3.3-V LVTTL : : 1 : Y
GND* : T10 : : : : 1 :
VCCINT : T11 : power : : 1.2V : :
GND : T12 : gnd : : : :
GND : T13 : gnd : : : :
GND : T14 : gnd : : : :
GND : T15 : gnd : : : :
VCCINT : T16 : power : : 1.2V : :
GND* : T17 : : : : 6 :
GND* : T18 : : : : 6 :
GND* : T19 : : : : 6 :
GND* : T20 : : : : 6 :
GND* : T21 : : : : 6 :
GND* : T22 : : : : 6 :
GND* : T23 : : : : 6 :
GND* : T24 : : : : 6 :
GND* : T25 : : : : 6 :
VCCIO6 : T26 : power : : 3.3V : 6 :
HEX4[1] : U1 : output : 3.3-V LVTTL : : 1 : Y
HEX4[2] : U2 : output : 3.3-V LVTTL : : 1 : Y
GND* : U3 : : : : 1 :
GND* : U4 : : : : 1 :
GND* : U5 : : : : 1 :
GND* : U6 : : : : 1 :
GND* : U7 : : : : 1 :
GND : U8 : gnd : : : :
HEX4[0] : U9 : output : 3.3-V LVTTL : : 1 : Y
GND* : U10 : : : : 1 :
VCCINT : U11 : power : : 1.2V : :
GND* : U12 : : : : 8 :
VCCINT : U13 : power : : 1.2V : :
VCCINT : U14 : power : : 1.2V : :
VCCINT : U15 : power : : 1.2V : :
VCCINT : U16 : power : : 1.2V : :
GND* : U17 : : : : 7 :
GND* : U18 : : : : 7 :
GND : U19 : gnd : : : :
GND* : U20 : : : : 6 :
GND* : U21 : : : : 6 :
HEX3[5] : U22 : output : 3.3-V LVTTL : : 6 : Y
GND* : U23 : : : : 6 :
GND* : U24 : : : : 6 :
GND* : U25 : : : : 6 :
GND* : U26 : : : : 6 :
GND* : V1 : : : : 1 :
GND* : V2 : : : : 1 :
GND* : V3 : : : : 1 :
GND* : V4 : : : : 1 :
GND* : V5 : : : : 1 :
GND* : V6 : : : : 1 :
GND* : V7 : : : : 1 :
VCCIO1 : V8 : power : : 3.3V : 1 :
GND* : V9 : : : : 8 :
GND* : V10 : : : : 8 :
GND* : V11 : : : : 8 :
VCCIO8 : V12 : power : : 3.3V : 8 :
HEX0[6] : V13 : output : 3.3-V LVTTL : : 8 : Y
HEX0[5] : V14 : output : 3.3-V LVTTL : : 8 : Y
VCCIO7 : V15 : power : : 3.3V : 7 :
VCCINT : V16 : power : : 1.2V : :
GND* : V17 : : : : 7 :
GND* : V18 : : : : 7 :
VCCIO6 : V19 : power : : 3.3V : 6 :
HEX1[0] : V20 : output : 3.3-V LVTTL : : 6 : Y
HEX1[1] : V21 : output : 3.3-V LVTTL : : 6 : Y
HEX2[1] : V22 : output : 3.3-V LVTTL : : 6 : Y
GND* : V23 : : : : 6 :
GND* : V24 : : : : 6 :
GND* : V25 : : : : 6 :
GND* : V26 : : : : 6 :
GND* : W1 : : : : 1 :
GND* : W2 : : : : 1 :
GND* : W3 : : : : 1 :
GND* : W4 : : : : 1 :
GND : W5 : gnd : : : :
GND* : W6 : : : : 1 :
GND_PLL1 : W7 : gnd : : : :
GND* : W8 : : : : 8 :
VCCIO8 : W9 : power : : 3.3V : 8 :
GND* : W10 : : : : 8 :
GND* : W11 : : : : 8 :
GND* : W12 : : : : 8 :
GND : W13 : gnd : : : :
GND : W14 : gnd : : : :
GND* : W15 : : : : 7 :
GND* : W16 : : : : 7 :
GND* : W17 : : : : 7 :
VCCIO7 : W18 : power : : 3.3V : 7 :
GND* : W19 : : : : 7 :
GND_PLL4 : W20 : gnd : : : :
HEX1[2] : W21 : output : 3.3-V LVTTL : : 6 : Y
GND : W22 : gnd : : : :
GND* : W23 : : : : 6 :
HEX3[6] : W24 : output : 3.3-V LVTTL : : 6 : Y
GND* : W25 : : : : 6 :
KEY[3] : W26 : input : 3.3-V LVTTL : : 6 : Y
GND* : Y1 : : : : 1 :
NC : Y2 : : : : :
GND* : Y3 : : : : 1 :
GND* : Y4 : : : : 1 :
GND* : Y5 : : : : 1 :
GND_PLL1 : Y6 : gnd : : : :
VCCD_PLL1 : Y7 : power : : 1.2V : :
GNDA_PLL1 : Y8 : gnd : : : :
GND : Y9 : gnd : : : :
GND* : Y10 : : : : 8 :
GND* : Y11 : : : : 8 :
GND* : Y12 : : : : 8 :
GND* : Y13 : : : : 7 :
GND* : Y14 : : : : 7 :
GND* : Y15 : : : : 7 :
GND* : Y16 : : : : 7 :
GND : Y17 : gnd : : : :
GND* : Y18 : : : : 7 :
GNDA_PLL4 : Y19 : gnd : : : :
VCCD_PLL4 : Y20 : power : : 1.2V : :
GND* : Y21 : : : : 6 :
HEX1[3] : Y22 : output : 3.3-V LVTTL : : 6 : Y
HEX3[0] : Y23 : output : 3.3-V LVTTL : : 6 : Y
HEX2[6] : Y24 : output : 3.3-V LVTTL : : 6 : Y
HEX3[4] : Y25 : output : 3.3-V LVTTL : : 6 : Y
HEX3[3] : Y26 : output : 3.3-V LVTTL : : 6 : Y
PS2_Demo/PS2_Demo.pof
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PS2_Demo/PS2_Demo.qpf
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# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
QUARTUS_VERSION = "6.0"
DATE = "20:46:28 November 09, 2006"
# Revisions
PROJECT_REVISION = "PS2_Demo"
PS2_Demo/PS2_Demo.qsf
+463
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@@ -0,0 +1,463 @@
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# PS2_Demo_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY PS2_Demo
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:46:28 NOVEMBER 09, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_location_assignment PIN_N25 -to SW[0]
set_location_assignment PIN_N26 -to SW[1]
set_location_assignment PIN_P25 -to SW[2]
set_location_assignment PIN_AE14 -to SW[3]
set_location_assignment PIN_AF14 -to SW[4]
set_location_assignment PIN_AD13 -to SW[5]
set_location_assignment PIN_AC13 -to SW[6]
set_location_assignment PIN_C13 -to SW[7]
set_location_assignment PIN_B13 -to SW[8]
set_location_assignment PIN_A13 -to SW[9]
set_location_assignment PIN_N1 -to SW[10]
set_location_assignment PIN_P1 -to SW[11]
set_location_assignment PIN_P2 -to SW[12]
set_location_assignment PIN_T7 -to SW[13]
set_location_assignment PIN_U3 -to SW[14]
set_location_assignment PIN_U4 -to SW[15]
set_location_assignment PIN_V1 -to SW[16]
set_location_assignment PIN_V2 -to SW[17]
set_location_assignment PIN_T6 -to DRAM_ADDR[0]
set_location_assignment PIN_V4 -to DRAM_ADDR[1]
set_location_assignment PIN_V3 -to DRAM_ADDR[2]
set_location_assignment PIN_W2 -to DRAM_ADDR[3]
set_location_assignment PIN_W1 -to DRAM_ADDR[4]
set_location_assignment PIN_U6 -to DRAM_ADDR[5]
set_location_assignment PIN_U7 -to DRAM_ADDR[6]
set_location_assignment PIN_U5 -to DRAM_ADDR[7]
set_location_assignment PIN_W4 -to DRAM_ADDR[8]
set_location_assignment PIN_W3 -to DRAM_ADDR[9]
set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
set_location_assignment PIN_V5 -to DRAM_ADDR[11]
set_location_assignment PIN_AE2 -to DRAM_BA_0
set_location_assignment PIN_AE3 -to DRAM_BA_1
set_location_assignment PIN_AB3 -to DRAM_CAS_N
set_location_assignment PIN_AA6 -to DRAM_CKE
set_location_assignment PIN_AA7 -to DRAM_CLK
set_location_assignment PIN_AC3 -to DRAM_CS_N
set_location_assignment PIN_V6 -to DRAM_DQ[0]
set_location_assignment PIN_AA2 -to DRAM_DQ[1]
set_location_assignment PIN_AA1 -to DRAM_DQ[2]
set_location_assignment PIN_Y3 -to DRAM_DQ[3]
set_location_assignment PIN_Y4 -to DRAM_DQ[4]
set_location_assignment PIN_R8 -to DRAM_DQ[5]
set_location_assignment PIN_T8 -to DRAM_DQ[6]
set_location_assignment PIN_V7 -to DRAM_DQ[7]
set_location_assignment PIN_W6 -to DRAM_DQ[8]
set_location_assignment PIN_AB2 -to DRAM_DQ[9]
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
set_location_assignment PIN_AA4 -to DRAM_DQ[11]
set_location_assignment PIN_AA3 -to DRAM_DQ[12]
set_location_assignment PIN_AC2 -to DRAM_DQ[13]
set_location_assignment PIN_AC1 -to DRAM_DQ[14]
set_location_assignment PIN_AA5 -to DRAM_DQ[15]
set_location_assignment PIN_AD2 -to DRAM_LDQM
set_location_assignment PIN_Y5 -to DRAM_UDQM
set_location_assignment PIN_AB4 -to DRAM_RAS_N
set_location_assignment PIN_AD3 -to DRAM_WE_N
set_location_assignment PIN_AC18 -to FL_ADDR[0]
set_location_assignment PIN_AB18 -to FL_ADDR[1]
set_location_assignment PIN_AE19 -to FL_ADDR[2]
set_location_assignment PIN_AF19 -to FL_ADDR[3]
set_location_assignment PIN_AE18 -to FL_ADDR[4]
set_location_assignment PIN_AF18 -to FL_ADDR[5]
set_location_assignment PIN_Y16 -to FL_ADDR[6]
set_location_assignment PIN_AA16 -to FL_ADDR[7]
set_location_assignment PIN_AD17 -to FL_ADDR[8]
set_location_assignment PIN_AC17 -to FL_ADDR[9]
set_location_assignment PIN_AE17 -to FL_ADDR[10]
set_location_assignment PIN_AF17 -to FL_ADDR[11]
set_location_assignment PIN_W16 -to FL_ADDR[12]
set_location_assignment PIN_W15 -to FL_ADDR[13]
set_location_assignment PIN_AC16 -to FL_ADDR[14]
set_location_assignment PIN_AD16 -to FL_ADDR[15]
set_location_assignment PIN_AE16 -to FL_ADDR[16]
set_location_assignment PIN_AC15 -to FL_ADDR[17]
set_location_assignment PIN_AB15 -to FL_ADDR[18]
set_location_assignment PIN_AA15 -to FL_ADDR[19]
set_location_assignment PIN_Y15 -to FL_ADDR[20]
set_location_assignment PIN_Y14 -to FL_ADDR[21]
set_location_assignment PIN_V17 -to FL_CE_N
set_location_assignment PIN_W17 -to FL_OE_N
set_location_assignment PIN_AD19 -to FL_DQ[0]
set_location_assignment PIN_AC19 -to FL_DQ[1]
set_location_assignment PIN_AF20 -to FL_DQ[2]
set_location_assignment PIN_AE20 -to FL_DQ[3]
set_location_assignment PIN_AB20 -to FL_DQ[4]
set_location_assignment PIN_AC20 -to FL_DQ[5]
set_location_assignment PIN_AF21 -to FL_DQ[6]
set_location_assignment PIN_AE21 -to FL_DQ[7]
set_location_assignment PIN_AA18 -to FL_RST_N
set_location_assignment PIN_AA17 -to FL_WE_N
set_location_assignment PIN_AF10 -to HEX0[0]
set_location_assignment PIN_AB12 -to HEX0[1]
set_location_assignment PIN_AC12 -to HEX0[2]
set_location_assignment PIN_AD11 -to HEX0[3]
set_location_assignment PIN_AE11 -to HEX0[4]
set_location_assignment PIN_V14 -to HEX0[5]
set_location_assignment PIN_V13 -to HEX0[6]
set_location_assignment PIN_V20 -to HEX1[0]
set_location_assignment PIN_V21 -to HEX1[1]
set_location_assignment PIN_W21 -to HEX1[2]
set_location_assignment PIN_Y22 -to HEX1[3]
set_location_assignment PIN_AA24 -to HEX1[4]
set_location_assignment PIN_AA23 -to HEX1[5]
set_location_assignment PIN_AB24 -to HEX1[6]
set_location_assignment PIN_AB23 -to HEX2[0]
set_location_assignment PIN_V22 -to HEX2[1]
set_location_assignment PIN_AC25 -to HEX2[2]
set_location_assignment PIN_AC26 -to HEX2[3]
set_location_assignment PIN_AB26 -to HEX2[4]
set_location_assignment PIN_AB25 -to HEX2[5]
set_location_assignment PIN_Y24 -to HEX2[6]
set_location_assignment PIN_Y23 -to HEX3[0]
set_location_assignment PIN_AA25 -to HEX3[1]
set_location_assignment PIN_AA26 -to HEX3[2]
set_location_assignment PIN_Y26 -to HEX3[3]
set_location_assignment PIN_Y25 -to HEX3[4]
set_location_assignment PIN_U22 -to HEX3[5]
set_location_assignment PIN_W24 -to HEX3[6]
set_location_assignment PIN_U9 -to HEX4[0]
set_location_assignment PIN_U1 -to HEX4[1]
set_location_assignment PIN_U2 -to HEX4[2]
set_location_assignment PIN_T4 -to HEX4[3]
set_location_assignment PIN_R7 -to HEX4[4]
set_location_assignment PIN_R6 -to HEX4[5]
set_location_assignment PIN_T3 -to HEX4[6]
set_location_assignment PIN_T2 -to HEX5[0]
set_location_assignment PIN_P6 -to HEX5[1]
set_location_assignment PIN_P7 -to HEX5[2]
set_location_assignment PIN_T9 -to HEX5[3]
set_location_assignment PIN_R5 -to HEX5[4]
set_location_assignment PIN_R4 -to HEX5[5]
set_location_assignment PIN_R3 -to HEX5[6]
set_location_assignment PIN_R2 -to HEX6[0]
set_location_assignment PIN_P4 -to HEX6[1]
set_location_assignment PIN_P3 -to HEX6[2]
set_location_assignment PIN_M2 -to HEX6[3]
set_location_assignment PIN_M3 -to HEX6[4]
set_location_assignment PIN_M5 -to HEX6[5]
set_location_assignment PIN_M4 -to HEX6[6]
set_location_assignment PIN_L3 -to HEX7[0]
set_location_assignment PIN_L2 -to HEX7[1]
set_location_assignment PIN_L9 -to HEX7[2]
set_location_assignment PIN_L6 -to HEX7[3]
set_location_assignment PIN_L7 -to HEX7[4]
set_location_assignment PIN_P9 -to HEX7[5]
set_location_assignment PIN_N9 -to HEX7[6]
set_location_assignment PIN_G26 -to KEY[0]
set_location_assignment PIN_N23 -to KEY[1]
set_location_assignment PIN_P23 -to KEY[2]
set_location_assignment PIN_W26 -to KEY[3]
set_location_assignment PIN_AE23 -to LEDR[0]
set_location_assignment PIN_AF23 -to LEDR[1]
set_location_assignment PIN_AB21 -to LEDR[2]
set_location_assignment PIN_AC22 -to LEDR[3]
set_location_assignment PIN_AD22 -to LEDR[4]
set_location_assignment PIN_AD23 -to LEDR[5]
set_location_assignment PIN_AD21 -to LEDR[6]
set_location_assignment PIN_AC21 -to LEDR[7]
set_location_assignment PIN_AA14 -to LEDR[8]
set_location_assignment PIN_Y13 -to LEDR[9]
set_location_assignment PIN_AA13 -to LEDR[10]
set_location_assignment PIN_AC14 -to LEDR[11]
set_location_assignment PIN_AD15 -to LEDR[12]
set_location_assignment PIN_AE15 -to LEDR[13]
set_location_assignment PIN_AF13 -to LEDR[14]
set_location_assignment PIN_AE13 -to LEDR[15]
set_location_assignment PIN_AE12 -to LEDR[16]
set_location_assignment PIN_AD12 -to LEDR[17]
set_location_assignment PIN_AE22 -to LEDG[0]
set_location_assignment PIN_AF22 -to LEDG[1]
set_location_assignment PIN_W19 -to LEDG[2]
set_location_assignment PIN_V18 -to LEDG[3]
set_location_assignment PIN_U18 -to LEDG[4]
set_location_assignment PIN_U17 -to LEDG[5]
set_location_assignment PIN_AA20 -to LEDG[6]
set_location_assignment PIN_Y18 -to LEDG[7]
set_location_assignment PIN_Y12 -to LEDG[8]
set_location_assignment PIN_D13 -to CLOCK_27
set_location_assignment PIN_N2 -to CLOCK_50
set_location_assignment PIN_P26 -to EXT_CLOCK
set_location_assignment PIN_D26 -to PS2_CLK
set_location_assignment PIN_C24 -to PS2_DAT
set_location_assignment PIN_C25 -to UART_RXD
set_location_assignment PIN_B25 -to UART_TXD
set_location_assignment PIN_K4 -to LCD_RW
set_location_assignment PIN_K3 -to LCD_EN
set_location_assignment PIN_K1 -to LCD_RS
set_location_assignment PIN_J1 -to LCD_DATA[0]
set_location_assignment PIN_J2 -to LCD_DATA[1]
set_location_assignment PIN_H1 -to LCD_DATA[2]
set_location_assignment PIN_H2 -to LCD_DATA[3]
set_location_assignment PIN_J4 -to LCD_DATA[4]
set_location_assignment PIN_J3 -to LCD_DATA[5]
set_location_assignment PIN_H4 -to LCD_DATA[6]
set_location_assignment PIN_H3 -to LCD_DATA[7]
set_location_assignment PIN_L4 -to LCD_ON
set_location_assignment PIN_K2 -to LCD_BLON
set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
set_location_assignment PIN_V10 -to SRAM_ADDR[10]
set_location_assignment PIN_V9 -to SRAM_ADDR[11]
set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
set_location_assignment PIN_W8 -to SRAM_ADDR[13]
set_location_assignment PIN_W10 -to SRAM_ADDR[14]
set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
set_location_assignment PIN_AD8 -to SRAM_DQ[0]
set_location_assignment PIN_AE6 -to SRAM_DQ[1]
set_location_assignment PIN_AF6 -to SRAM_DQ[2]
set_location_assignment PIN_AA9 -to SRAM_DQ[3]
set_location_assignment PIN_AA10 -to SRAM_DQ[4]
set_location_assignment PIN_AB10 -to SRAM_DQ[5]
set_location_assignment PIN_AA11 -to SRAM_DQ[6]
set_location_assignment PIN_Y11 -to SRAM_DQ[7]
set_location_assignment PIN_AE7 -to SRAM_DQ[8]
set_location_assignment PIN_AF7 -to SRAM_DQ[9]
set_location_assignment PIN_AE8 -to SRAM_DQ[10]
set_location_assignment PIN_AF8 -to SRAM_DQ[11]
set_location_assignment PIN_W11 -to SRAM_DQ[12]
set_location_assignment PIN_W12 -to SRAM_DQ[13]
set_location_assignment PIN_AC9 -to SRAM_DQ[14]
set_location_assignment PIN_AC10 -to SRAM_DQ[15]
set_location_assignment PIN_AE10 -to SRAM_WE_N
set_location_assignment PIN_AD10 -to SRAM_OE_N
set_location_assignment PIN_AF9 -to SRAM_UB_N
set_location_assignment PIN_AE9 -to SRAM_LB_N
set_location_assignment PIN_AC11 -to SRAM_CE_N
set_location_assignment PIN_K7 -to OTG_ADDR[0]
set_location_assignment PIN_F2 -to OTG_ADDR[1]
set_location_assignment PIN_F1 -to OTG_CS_N
set_location_assignment PIN_G2 -to OTG_RD_N
set_location_assignment PIN_G1 -to OTG_WR_N
set_location_assignment PIN_G5 -to OTG_RST_N
set_location_assignment PIN_F4 -to OTG_DATA[0]
set_location_assignment PIN_D2 -to OTG_DATA[1]
set_location_assignment PIN_D1 -to OTG_DATA[2]
set_location_assignment PIN_F7 -to OTG_DATA[3]
set_location_assignment PIN_J5 -to OTG_DATA[4]
set_location_assignment PIN_J8 -to OTG_DATA[5]
set_location_assignment PIN_J7 -to OTG_DATA[6]
set_location_assignment PIN_H6 -to OTG_DATA[7]
set_location_assignment PIN_E2 -to OTG_DATA[8]
set_location_assignment PIN_E1 -to OTG_DATA[9]
set_location_assignment PIN_K6 -to OTG_DATA[10]
set_location_assignment PIN_K5 -to OTG_DATA[11]
set_location_assignment PIN_G4 -to OTG_DATA[12]
set_location_assignment PIN_G3 -to OTG_DATA[13]
set_location_assignment PIN_J6 -to OTG_DATA[14]
set_location_assignment PIN_K8 -to OTG_DATA[15]
set_location_assignment PIN_B3 -to OTG_INT0
set_location_assignment PIN_C3 -to OTG_INT1
set_location_assignment PIN_C2 -to OTG_DACK0_N
set_location_assignment PIN_B2 -to OTG_DACK1_N
set_location_assignment PIN_F6 -to OTG_DREQ0
set_location_assignment PIN_E5 -to OTG_DREQ1
set_location_assignment PIN_F3 -to OTG_FSPEED
set_location_assignment PIN_G6 -to OTG_LSPEED
set_location_assignment PIN_B14 -to TDI
set_location_assignment PIN_A14 -to TCS
set_location_assignment PIN_D14 -to TCK
set_location_assignment PIN_F14 -to TDO
set_location_assignment PIN_C4 -to TD_RESET
set_location_assignment PIN_C8 -to VGA_R[0]
set_location_assignment PIN_F10 -to VGA_R[1]
set_location_assignment PIN_G10 -to VGA_R[2]
set_location_assignment PIN_D9 -to VGA_R[3]
set_location_assignment PIN_C9 -to VGA_R[4]
set_location_assignment PIN_A8 -to VGA_R[5]
set_location_assignment PIN_H11 -to VGA_R[6]
set_location_assignment PIN_H12 -to VGA_R[7]
set_location_assignment PIN_F11 -to VGA_R[8]
set_location_assignment PIN_E10 -to VGA_R[9]
set_location_assignment PIN_B9 -to VGA_G[0]
set_location_assignment PIN_A9 -to VGA_G[1]
set_location_assignment PIN_C10 -to VGA_G[2]
set_location_assignment PIN_D10 -to VGA_G[3]
set_location_assignment PIN_B10 -to VGA_G[4]
set_location_assignment PIN_A10 -to VGA_G[5]
set_location_assignment PIN_G11 -to VGA_G[6]
set_location_assignment PIN_D11 -to VGA_G[7]
set_location_assignment PIN_E12 -to VGA_G[8]
set_location_assignment PIN_D12 -to VGA_G[9]
set_location_assignment PIN_J13 -to VGA_B[0]
set_location_assignment PIN_J14 -to VGA_B[1]
set_location_assignment PIN_F12 -to VGA_B[2]
set_location_assignment PIN_G12 -to VGA_B[3]
set_location_assignment PIN_J10 -to VGA_B[4]
set_location_assignment PIN_J11 -to VGA_B[5]
set_location_assignment PIN_C11 -to VGA_B[6]
set_location_assignment PIN_B11 -to VGA_B[7]
set_location_assignment PIN_C12 -to VGA_B[8]
set_location_assignment PIN_B12 -to VGA_B[9]
set_location_assignment PIN_B8 -to VGA_CLK
set_location_assignment PIN_D6 -to VGA_BLANK
set_location_assignment PIN_A7 -to VGA_HS
set_location_assignment PIN_D8 -to VGA_VS
set_location_assignment PIN_B7 -to VGA_SYNC
set_location_assignment PIN_A6 -to I2C_SCLK
set_location_assignment PIN_B6 -to I2C_SDAT
set_location_assignment PIN_J9 -to TD_DATA[0]
set_location_assignment PIN_E8 -to TD_DATA[1]
set_location_assignment PIN_H8 -to TD_DATA[2]
set_location_assignment PIN_H10 -to TD_DATA[3]
set_location_assignment PIN_G9 -to TD_DATA[4]
set_location_assignment PIN_F9 -to TD_DATA[5]
set_location_assignment PIN_D7 -to TD_DATA[6]
set_location_assignment PIN_C7 -to TD_DATA[7]
set_location_assignment PIN_D5 -to TD_HS
set_location_assignment PIN_K9 -to TD_VS
set_location_assignment PIN_C5 -to AUD_ADCLRCK
set_location_assignment PIN_B5 -to AUD_ADCDAT
set_location_assignment PIN_C6 -to AUD_DACLRCK
set_location_assignment PIN_A4 -to AUD_DACDAT
set_location_assignment PIN_A5 -to AUD_XCK
set_location_assignment PIN_B4 -to AUD_BCLK
set_location_assignment PIN_D17 -to ENET_DATA[0]
set_location_assignment PIN_C17 -to ENET_DATA[1]
set_location_assignment PIN_B18 -to ENET_DATA[2]
set_location_assignment PIN_A18 -to ENET_DATA[3]
set_location_assignment PIN_B17 -to ENET_DATA[4]
set_location_assignment PIN_A17 -to ENET_DATA[5]
set_location_assignment PIN_B16 -to ENET_DATA[6]
set_location_assignment PIN_B15 -to ENET_DATA[7]
set_location_assignment PIN_B20 -to ENET_DATA[8]
set_location_assignment PIN_A20 -to ENET_DATA[9]
set_location_assignment PIN_C19 -to ENET_DATA[10]
set_location_assignment PIN_D19 -to ENET_DATA[11]
set_location_assignment PIN_B19 -to ENET_DATA[12]
set_location_assignment PIN_A19 -to ENET_DATA[13]
set_location_assignment PIN_E18 -to ENET_DATA[14]
set_location_assignment PIN_D18 -to ENET_DATA[15]
set_location_assignment PIN_B24 -to ENET_CLK
set_location_assignment PIN_A21 -to ENET_CMD
set_location_assignment PIN_A23 -to ENET_CS_N
set_location_assignment PIN_B21 -to ENET_INT
set_location_assignment PIN_A22 -to ENET_RD_N
set_location_assignment PIN_B22 -to ENET_WR_N
set_location_assignment PIN_B23 -to ENET_RST_N
set_location_assignment PIN_AE24 -to IRDA_TXD
set_location_assignment PIN_AE25 -to IRDA_RXD
set_location_assignment PIN_AD24 -to SD_DAT
set_location_assignment PIN_AC23 -to SD_DAT3
set_location_assignment PIN_Y21 -to SD_CMD
set_location_assignment PIN_AD25 -to SD_CLK
set_location_assignment PIN_D25 -to GPIO_0[0]
set_location_assignment PIN_J22 -to GPIO_0[1]
set_location_assignment PIN_E26 -to GPIO_0[2]
set_location_assignment PIN_E25 -to GPIO_0[3]
set_location_assignment PIN_F24 -to GPIO_0[4]
set_location_assignment PIN_F23 -to GPIO_0[5]
set_location_assignment PIN_J21 -to GPIO_0[6]
set_location_assignment PIN_J20 -to GPIO_0[7]
set_location_assignment PIN_F25 -to GPIO_0[8]
set_location_assignment PIN_F26 -to GPIO_0[9]
set_location_assignment PIN_N18 -to GPIO_0[10]
set_location_assignment PIN_P18 -to GPIO_0[11]
set_location_assignment PIN_G23 -to GPIO_0[12]
set_location_assignment PIN_G24 -to GPIO_0[13]
set_location_assignment PIN_K22 -to GPIO_0[14]
set_location_assignment PIN_G25 -to GPIO_0[15]
set_location_assignment PIN_H23 -to GPIO_0[16]
set_location_assignment PIN_H24 -to GPIO_0[17]
set_location_assignment PIN_J23 -to GPIO_0[18]
set_location_assignment PIN_J24 -to GPIO_0[19]
set_location_assignment PIN_H25 -to GPIO_0[20]
set_location_assignment PIN_H26 -to GPIO_0[21]
set_location_assignment PIN_H19 -to GPIO_0[22]
set_location_assignment PIN_K18 -to GPIO_0[23]
set_location_assignment PIN_K19 -to GPIO_0[24]
set_location_assignment PIN_K21 -to GPIO_0[25]
set_location_assignment PIN_K23 -to GPIO_0[26]
set_location_assignment PIN_K24 -to GPIO_0[27]
set_location_assignment PIN_L21 -to GPIO_0[28]
set_location_assignment PIN_L20 -to GPIO_0[29]
set_location_assignment PIN_J25 -to GPIO_0[30]
set_location_assignment PIN_J26 -to GPIO_0[31]
set_location_assignment PIN_L23 -to GPIO_0[32]
set_location_assignment PIN_L24 -to GPIO_0[33]
set_location_assignment PIN_L25 -to GPIO_0[34]
set_location_assignment PIN_L19 -to GPIO_0[35]
set_location_assignment PIN_K25 -to GPIO_1[0]
set_location_assignment PIN_K26 -to GPIO_1[1]
set_location_assignment PIN_M22 -to GPIO_1[2]
set_location_assignment PIN_M23 -to GPIO_1[3]
set_location_assignment PIN_M19 -to GPIO_1[4]
set_location_assignment PIN_M20 -to GPIO_1[5]
set_location_assignment PIN_N20 -to GPIO_1[6]
set_location_assignment PIN_M21 -to GPIO_1[7]
set_location_assignment PIN_M24 -to GPIO_1[8]
set_location_assignment PIN_M25 -to GPIO_1[9]
set_location_assignment PIN_N24 -to GPIO_1[10]
set_location_assignment PIN_P24 -to GPIO_1[11]
set_location_assignment PIN_R25 -to GPIO_1[12]
set_location_assignment PIN_R24 -to GPIO_1[13]
set_location_assignment PIN_R20 -to GPIO_1[14]
set_location_assignment PIN_T22 -to GPIO_1[15]
set_location_assignment PIN_T23 -to GPIO_1[16]
set_location_assignment PIN_T24 -to GPIO_1[17]
set_location_assignment PIN_T25 -to GPIO_1[18]
set_location_assignment PIN_T18 -to GPIO_1[19]
set_location_assignment PIN_T21 -to GPIO_1[20]
set_location_assignment PIN_T20 -to GPIO_1[21]
set_location_assignment PIN_U26 -to GPIO_1[22]
set_location_assignment PIN_U25 -to GPIO_1[23]
set_location_assignment PIN_U23 -to GPIO_1[24]
set_location_assignment PIN_U24 -to GPIO_1[25]
set_location_assignment PIN_R19 -to GPIO_1[26]
set_location_assignment PIN_T19 -to GPIO_1[27]
set_location_assignment PIN_U20 -to GPIO_1[28]
set_location_assignment PIN_U21 -to GPIO_1[29]
set_location_assignment PIN_V26 -to GPIO_1[30]
set_location_assignment PIN_V25 -to GPIO_1[31]
set_location_assignment PIN_V24 -to GPIO_1[32]
set_location_assignment PIN_V23 -to GPIO_1[33]
set_location_assignment PIN_W25 -to GPIO_1[34]
set_location_assignment PIN_W23 -to GPIO_1[35]
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_FILE Altera_UP_PS2.v
set_global_assignment -name VERILOG_FILE Altera_UP_PS2_Command_Out.v
set_global_assignment -name VERILOG_FILE Altera_UP_PS2_Data_In.v
set_global_assignment -name VERILOG_FILE PS2_Demo.v
set_global_assignment -name VERILOG_FILE Hexadecimal_To_Seven_Segment.v
PS2_Demo/PS2_Demo.qws
+30
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@@ -0,0 +1,30 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
ptn_Child4=Document-3
ptn_Child5=Document-4
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=PS2_Demo.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
[ProjectWorkspace.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=PS2_Controller.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
PS2_Demo/PS2_Demo.sof
BIN
View File
Binary file not shown.
PS2_Demo/PS2_Demo.v
+129
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@@ -0,0 +1,129 @@
module PS2_Demo (
// Inputs
CLOCK_50,
KEY,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input [3:0] KEY;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [7:0] ps2_key_data;
wire ps2_key_pressed;
// Internal Registers
reg [7:0] last_data_received;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (KEY[0] == 1'b0)
last_data_received <= 8'h00;
else if (ps2_key_pressed == 1'b1)
last_data_received <= ps2_key_data;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign HEX2 = 7'h7F;
assign HEX3 = 7'h7F;
assign HEX4 = 7'h7F;
assign HEX5 = 7'h7F;
assign HEX6 = 7'h7F;
assign HEX7 = 7'h7F;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
PS2_Controller PS2 (
// Inputs
.CLOCK_50 (CLOCK_50),
.reset (~KEY[0]),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.received_data (ps2_key_data),
.received_data_en (ps2_key_pressed)
);
Hexadecimal_To_Seven_Segment Segment0 (
// Inputs
.hex_number (last_data_received[3:0]),
// Bidirectional
// Outputs
.seven_seg_display (HEX0)
);
Hexadecimal_To_Seven_Segment Segment1 (
// Inputs
.hex_number (last_data_received[7:4]),
// Bidirectional
// Outputs
.seven_seg_display (HEX1)
);
endmodule
PS2_Demo/PS2_Demo_assignment_defaults.qdf
+428
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@@ -0,0 +1,428 @@
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name INCREMENTAL_COMPILATION -value OFF
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY On
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION On
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE On
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths"
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING Off
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
set_global_assignment -name AUTO_PACKED_REGISTERS Off
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL93
set_global_assignment -name FAMILY -value Stratix
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME Off
set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO On
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name ADV_NETLIST_OPT_METASTABLE_REGS 2
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name SUPPRESS_REG_MINIMIZATION_MSG Off
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
set_global_assignment -name ENABLE_CLOCK_LATENCY Off
set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
set_global_assignment -name DO_MIN_ANALYSIS Off
set_global_assignment -name DO_MIN_TIMING Off
set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name SMART_RECOMPILE Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_HCII_COMPARE Off
set_global_assignment -name HCII_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name NUM_PARALLEL_PROCESSORS 1
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name DUTY_CYCLE 50 -section_id ?
set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
PS_2 Controller.pdf
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README.md
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# FPGA-PS2
How to interface a mouse with Basys 3 FPGA
How to interface a mouse with FPGA
Source:
https://www.fpga4student.com/2017/12/how-to-interface-mouse-with-FPGA.html
* Source: https://www.fpga4student.com/2017/12/how-to-interface-mouse-with-FPGA.html
mouse with Basys 3 FPGA
* Folder PS2_Demo contains demon from: http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/ps2/ps2.html
This is the ready to use Quartus project