imants/FPGA-Mandelbrot-Set
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Imants Pulkstenis 4a0ccbb372 new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00
7segment_tb.v
Initial file upload
2019-07-12 12:19:06 +03:00
7segment.v
Initial file upload
2019-07-12 12:19:06 +03:00
Basys3_Master.xdc
new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00
blockram.v
new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00
clock_divider_param_tb.v
Initial file upload
2019-07-12 12:19:06 +03:00
clock_divider_param.v
Initial file upload
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clock_enable_param.v
Initial file upload
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clock_enable_tb.v
Initial file upload
2019-07-12 12:19:06 +03:00
com_to_mem_FSM_hex.v
Initial file upload
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com_to_mem_module.v
Initial file upload
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com_to_mem_tb.v
Initial file upload
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debounce_switch.v
Initial file upload
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horizontal_counter.v
Initial file upload
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mux.v
new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00
pattern_gen_tb.v
Initial file upload
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pattern_gen.v
Initial file upload
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README.md
new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00
top_tb.v
Initial file upload
2019-07-12 12:19:06 +03:00
top.v
new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00
UART_Loopback_module.v
Initial file upload
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UART_Loopback_tb.v
Initial file upload
2019-07-12 12:19:06 +03:00
UART_RX.v
Initial file upload
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UART_TX.v
Initial file upload
2019-07-12 12:19:06 +03:00
vertical_counter.v
Initial file upload
2019-07-12 12:19:06 +03:00
vga_module.v
new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00

README.md

FPGA Mandelbrot Set on Digilent Basys3 Xilinx Artix 7 (Not finished)

Mandelbrot set visualization

picture

I will try make Cornell University ECE 5760: Laboratory 3 Mandelbrot set visualization. http://people.ece.cornell.edu/land/courses/ece5760/LABS/s2019/lab3_mandelbrot.html

Lectures:

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Description
Mandelbrot set visualization
Readme
57 KiB
Languages
Verilog 83.3%
Tcl 13.8%
MATLAB 2.9%