new MUX file, VGA memory splited in 15 seperate parts

Basys3_Master.xdc

@@ -3,18 +3,22 @@
 ## - uncomment the lines corresponding to used pins
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
 
+## CFGBVS
+set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+
 ## Clock signal
-#set_property PACKAGE_PIN W5 [get_ports clk]							
-	#set_property IOSTANDARD LVCMOS33 [get_ports clk]
-	#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+set_property PACKAGE_PIN W5 [get_ports clk]							
+	set_property IOSTANDARD LVCMOS33 [get_ports clk]
+	create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
  
 ## Switches
-#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
-#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
-#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
 #set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
 	#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
 #set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
@@ -79,32 +83,32 @@
 	
 	
 ##7 segment display
-#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
-#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
-#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
-#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
-#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
-#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
-#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+set_property PACKAGE_PIN U7 [get_ports {seg[6]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
 
 #set_property PACKAGE_PIN V7 [get_ports dp]							
 	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
 
-#set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
-#set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
-#set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
-#set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
+	set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
 
 
 ##Buttons
@@ -233,41 +237,41 @@
 
 
 ##VGA Connector
-#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
-#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
-#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
-#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
-#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
-#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
-#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
-#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
-#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
-#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
-#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
-#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]				
-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
-#set_property PACKAGE_PIN P19 [get_ports Hsync]						
-	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
-#set_property PACKAGE_PIN R19 [get_ports Vsync]						
-	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
+set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
+set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
+set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
+set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
+set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
+set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
+set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
+set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
+set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
+set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
+set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
+set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]				
+	set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
+set_property PACKAGE_PIN P19 [get_ports Hsync]						
+	set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
+set_property PACKAGE_PIN R19 [get_ports Vsync]						
+	set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
 
 
 ##USB-RS232 Interface
-#set_property PACKAGE_PIN B18 [get_ports RsRx]						
-	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
-#set_property PACKAGE_PIN A18 [get_ports RsTx]						
-	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
+set_property PACKAGE_PIN B18 [get_ports RsRx]						
+	set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
+set_property PACKAGE_PIN A18 [get_ports RsTx]						
+	set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
 
 
 ##USB HID (PS/2)

README.md

@@ -1,4 +1,4 @@
-# FPGA-Mandelbrot-Set (Not finished)
+# FPGA Mandelbrot Set on Digilent Basys3 Xilinx Artix 7 (Not finished)
 Mandelbrot set visualization 
 
 ![picture](http://people.ece.cornell.edu/land/courses/ece5760/LABS/s2019/lab3_mandelbrot_rectangle.png)

blockram.v

@@ -7,10 +7,10 @@
 // Dual-Port Block RAM with Two Write Ports
 // File: rams_tdp_rf_rf.v
 
-module rams_tdp_rf_rf #( parameter
-    DEPTH =  307_200,//76_800,
-    ADDR_WIDTH = 17, 
-    DATA_WIDTH = 8 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
+module blockram #( parameter
+    DEPTH =  4_800,//307_200,//76_800,
+    ADDR_WIDTH = 13, 
+    DATA_WIDTH = 12 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
 
 input clka,clkb,ena,enb,wea,web;
 input [ADDR_WIDTH-1:0] addra,addrb;

mux.v

@@ -0,0 +1,50 @@
+module mux #( parameter
+    DATA_WIDTH = 12, 
+    SELECT_WIDTH = 4
+)(
+    input [SELECT_WIDTH - 1 :0]     select,
+    input [DATA_WIDTH - 1 :0]       d0,
+    input [DATA_WIDTH - 1 :0]       d1,
+    input [DATA_WIDTH - 1 :0]       d2,
+    input [DATA_WIDTH - 1 :0]       d3,
+    input [DATA_WIDTH - 1 :0]       d4,
+    input [DATA_WIDTH - 1 :0]       d5,
+    input [DATA_WIDTH - 1 :0]       d6,
+    input [DATA_WIDTH - 1 :0]       d7,
+    input [DATA_WIDTH - 1 :0]       d8,
+    input [DATA_WIDTH - 1 :0]       d9,
+    input [DATA_WIDTH - 1 :0]       d10,
+    input [DATA_WIDTH - 1 :0]       d11,
+    input [DATA_WIDTH - 1 :0]       d12,
+    input [DATA_WIDTH - 1 :0]       d13,
+    input [DATA_WIDTH - 1 :0]       d14,
+    output[DATA_WIDTH - 1 :0]      o_q  
+);
+
+reg [DATA_WIDTH - 1 :0]      q ;
+
+always @*
+begin
+   case( select )
+       'd0 : q <= d0;
+       'd1 : q <= d1;
+       'd2 : q <= d2;
+       'd3 : q <= d3;
+       'd4 : q <= d4;
+       'd5 : q <= d5;
+       'd6 : q <= d6;
+       'd7 : q <= d7;
+       'd8 : q <= d8;
+       'd9 : q <= d9;
+       'd10 : q <= d10;
+       'd11 : q <= d11;
+       'd12 : q <= d12;
+       'd13 : q <= d13;
+       'd14 : q <= d14;
+       default : q <= 12'd0;
+   endcase
+end
+
+assign o_q = q;
+
+endmodule

top.v

@@ -1,15 +1,6 @@
 //      TOP module 
 //       
 //      
-// `include "clock_divider_param.v"
-// `include "clock_enable_param.v"
-// `include "blockram.v"
-// `include "pattern_gen.v"
-// `include "vga_module.v"
-// `include "horizontal_counter.v"
-// `include "vertical_counter.v"
-
-
 
 module top #( parameter
     //pattern generator paremater
@@ -18,9 +9,9 @@ module top #( parameter
     WAIT = 1,
     WAIT_WIDTH = 2,
     //memory parameters
-    ADDR_WIDTH = 17, // 19, //
+    ADDR_WIDTH = 13, // 
     DATA_WIDTH = 12, 
-    DEPTH =  76_800, // 307_200,//
+    DEPTH =  5_120, // ( 320 * 16 ) 
     //VGA parameters
     HSYNC_CLKS = 800,
     HSYNC_DISPLAY = 640,
@@ -34,8 +25,7 @@ module top #( parameter
     VSYNC_BACK_PORCH = 29
 )(
     input           clk,
-    output  [11:0]  led,
-    output  [1:0]   ledc,   // led camera configuration indicator
+//    output  [11:0]  led,
     //VGA  inputs outputs
     output [3:0]    vgaRed,
     output [3:0]    vgaBlue,
@@ -49,32 +39,41 @@ module top #( parameter
     // 7 segment
     output  [6:0]   seg, 
     output  [3:0]   an  
-
-
     );
 
 //------internal wires and registers--------
- wire w_enable;
- wire pixel_clk;
+wire w_enable;
+ 
+wire w_write;
 
- wire clk50;    
+wire [ADDR_WIDTH-1:0] w_addr_wr;
+wire [DATA_WIDTH-1:0] w_data_wr;
 
- wire w_write;
+wire [ADDR_WIDTH-1:0] w_com_addr_wr;
+wire [DATA_WIDTH-1:0] w_com_data_wr;
+wire w_com_write;
+wire [ADDR_WIDTH-1:0] w_com_addr_rd;
 
- wire [ADDR_WIDTH-1:0] w_addr_wr;
- wire [DATA_WIDTH-1:0] w_data_wr;
-
- wire [ADDR_WIDTH-1:0] w_com_addr_wr;
- wire [DATA_WIDTH-1:0] w_com_data_wr;
- wire w_com_write;
- wire [ADDR_WIDTH-1:0] w_com_addr_rd;
+wire [3:0] w_vga_line_mux;
 
 //  wire [ADDR_WIDTH-1:0] w_addrb;
 
- wire [ADDR_WIDTH-1:0] w_addr_rd;
- wire [DATA_WIDTH-1:0] w_data_rd;
-
- 
+wire [DATA_WIDTH-1:0] w_data_rd;
+wire [DATA_WIDTH-1:0] w_data_rd0;
+wire [DATA_WIDTH-1:0] w_data_rd1;
+wire [DATA_WIDTH-1:0] w_data_rd2;
+wire [DATA_WIDTH-1:0] w_data_rd3;
+wire [DATA_WIDTH-1:0] w_data_rd4;
+wire [DATA_WIDTH-1:0] w_data_rd5;
+wire [DATA_WIDTH-1:0] w_data_rd6;
+wire [DATA_WIDTH-1:0] w_data_rd7;
+wire [DATA_WIDTH-1:0] w_data_rd8;
+wire [DATA_WIDTH-1:0] w_data_rd9;
+wire [DATA_WIDTH-1:0] w_data_rd10;
+wire [DATA_WIDTH-1:0] w_data_rd11;
+wire [DATA_WIDTH-1:0] w_data_rd12;
+wire [DATA_WIDTH-1:0] w_data_rd13;
+wire [DATA_WIDTH-1:0] w_data_rd14;
 
 //-----sub modules--------------------------
 clock_enable_param #(
@@ -94,7 +93,6 @@ clock_divider #(
 );
 
 
-
 pattern_gen #( 
     .DEPTH(DEPTH),
     .ADDR_WIDTH(ADDR_WIDTH),
@@ -109,27 +107,6 @@ pattern_gen #(
     .o_write(w_write)
 );
 
-rams_tdp_rf_rf #( 
-    .DEPTH(DEPTH),
-    .ADDR_WIDTH(ADDR_WIDTH), 
-    .DATA_WIDTH(DATA_WIDTH)) 
-bram3(
-    // -------------------------PORT A
-    .clka(clk),
-    .ena(  1'b1  /*w_enable*/),
-    .wea( w_wea_bram ),
-    .addra( w_addra_bram ),
-    .dia( w_dia_bram ),
-    .doa( w_doa_bram ),
-
-    //---------------------------PORT B
-    .clkb(clk),
-    .addrb( w_addr_rd ),
-    .enb(w_enable),
-    //.web(),
-    //.dib(),
-    .dob(w_data_rd));
-
 
 vga_module #(  
         .ADDR_WIDTH(ADDR_WIDTH),
@@ -153,35 +130,34 @@ vga_module #(
     .o_Hsync(Hsync),
     .o_Vsync(Vsync),
     .o_display(),
+    .o_line_mux(w_vga_line_mux),
     .o_addr_rd(w_addr_rd),
-    .o_data_rd(w_data_rd)
+    .o_data_rd(r_data_rd)
    );
 
-com_to_mem #( 
-    .WAIT(WAIT),
-    .WAIT_WIDTH(WAIT_WIDTH),
-    .ADDR_WIDTH(ADDR_WIDTH),
-    .DATA_WIDTH(DATA_WIDTH), 
-    .DEPTH(DEPTH)
-) com_to_mem1 (
-    .clk(clk),
-    .sw(sw[0]),
-    //.i_data_rd(w_doa_bram),
-    .i_enable(w_enable),
-    .o_addr_wr(w_com_addr_wr),
-    .o_addr_rd(w_com_addr_rd),
-    .o_data_wr(w_com_data_wr),
-    .o_write(w_com_write),
-    .RsRx(RsRx),         // UART RX Data
-    .RsTx(RsTx),        // UART TX Data
-    .seg(seg), 
-    .an(an),
-    .o_addr_wr_reg(w_addr_com_wr_reg),
-    .o_data_reg(w_data_com_reg),
-    .o_we_reg(w_we_com_reg)
-    );
-
-
+// com_to_mem #( 
+//     .WAIT(WAIT),
+//     .WAIT_WIDTH(WAIT_WIDTH),
+//     .ADDR_WIDTH(ADDR_WIDTH),
+//     .DATA_WIDTH(DATA_WIDTH), 
+//     .DEPTH(DEPTH)
+// ) com_to_mem1 (
+//     .clk(clk),
+//     .sw(sw[0]),
+//     //.i_data_rd(w_doa_bram),
+//     .i_enable(w_enable),
+//     .o_addr_wr(w_com_addr_wr),
+//     .o_addr_rd(w_com_addr_rd),
+//     .o_data_wr(w_com_data_wr),
+//     .o_write(w_com_write),
+//     .RsRx(RsRx),         // UART RX Data
+//     .RsTx(RsTx),        // UART TX Data
+//     .seg(seg), 
+//     .an(an),
+//     .o_addr_wr_reg(w_addr_com_wr_reg),
+//     .o_data_reg(w_data_com_reg),
+//     .o_we_reg(w_we_com_reg)
+//     );
 
 // debounce_switch debounce_switch_reset(
 //     .clk(clk),
@@ -189,7 +165,359 @@ com_to_mem #(
 //     .o_switch(w_reset_default)
 // );
 
+mux #(
+    .DATA_WIDTH(DATA_WIDTH), 
+    .SELECT_WIDTH('d4)) 
+mux1(
+    select(w_vga_line_mux),
+    d0(w_data_rd0),
+    d1(w_data_rd1),
+    d2(w_data_rd2),
+    d3(w_data_rd3),
+    d4(w_data_rd4),
+    d5(w_data_rd5),
+    d6(w_data_rd6),
+    d7(w_data_rd7),
+    d8(w_data_rd8),
+    d9(w_data_rd9),
+    d10(w_data_rd10),
+    d11(w_data_rd11),
+    d12(w_data_rd12),
+    d13(w_data_rd13),
+    d14(w_data_rd14),
+    q(w_data_rd));
 
 
 
+//-------------- memory modules-------------------------
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram0(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd0));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram1(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd1));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram2(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd2));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram3(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd3));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram4(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd4));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram5(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd5));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram6(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd6));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram7(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd7));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram8(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd8));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram9(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd9));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram10(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd10));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram11(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd11));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram12(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd12));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram13(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd13));
+
+
+blockram #( 
+    .DEPTH(DEPTH),
+    .ADDR_WIDTH(ADDR_WIDTH), 
+    .DATA_WIDTH(DATA_WIDTH)) 
+bram14(
+    // -------------------------PORT A (write)
+    .clka(clk),
+    .ena(  1'b1  /*w_enable*/),
+    .wea( w_write ),
+    .addra( w_addr_wr ),
+    .dia( w_data_wr ),
+    .doa(   ),
+
+    //---------------------------PORT B (read)
+    .clkb(clk),
+    .addrb( w_addr_rd ),
+    .enb(w_enable),
+    //.web(),
+    //.dib(),
+    .dob(w_data_rd14));
+
 endmodule

vga_module.v

@@ -1,8 +1,8 @@
 module vga_module#( 
     parameter
-        ADDR_WIDTH = 17, 
+        ADDR_WIDTH = 13, 
         DATA_WIDTH = 12, 
-        DEPTH =  76_800, // 307_200,//
+        DEPTH =  4_800, // 307_200,//
         HSYNC_CLKS = 800,
         HSYNC_DISPLAY = 640,
         HSYNC_PULSE = 96,
@@ -21,6 +21,7 @@ module vga_module#(
         output o_Hsync,
         output o_Vsync,
         output o_display,
+        output [3:0] o_line_mux,
         output [ADDR_WIDTH-1:0] o_addr_rd,
         input [DATA_WIDTH-1:0] o_data_rd
         );
@@ -28,7 +29,7 @@ module vga_module#(
 //-------Internal registers and wires--------------
 wire w_v_display;
 wire w_h_display;
-wire [9:0] pixel;
+wire [9:0] column;
 wire [8:0] line;
 
 //-------sub modules-------------------------------
@@ -43,7 +44,7 @@ horizontal_counter #(
         .clk(clk),
         .o_Hsync(o_Hsync),
         .o_h_display(w_h_display),
-        .o_h_pixel(pixel)
+        .o_h_pixel(column)
         );
 
 vertical_counter #( 
@@ -66,11 +67,12 @@ assign o_vgaBlue = o_display ? o_data_rd[3:0] : 4'h0;
 assign o_vgaGreen = o_display ? o_data_rd[7:4] : 4'h0;
 
 /*
-assign o_addr_rd = (((line*HSYNC_DISPLAY) + pixel + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ?
-                        'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + pixel[9:1] + 1 ;   // get next pixel
+assign o_addr_rd = (((line*HSYNC_DISPLAY) + column + 1) == HSYNC_DISPLAY * VSYNC_DISPLAY ) ?
+                        'h0 : ((line[8:1]) * HSYNC_DISPLAY/2 ) + column[9:1] + 1 ;   // get next pixel
 */
 assign o_addr_rd =  
-                    ((line[8:1]) * 'd320 ) + pixel[9:1];// + 1;
+                    ((line[4:1]) * 'd320 ) + column[9:1];// + 1;
 
+assign o_line_mux = line[8:5];
 
 endmodule