195 lines
4.0 KiB
Verilog
195 lines
4.0 KiB
Verilog
// TOP module
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//
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//
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// `include "clock_divider_param.v"
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// `include "clock_enable_param.v"
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// `include "blockram.v"
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// `include "pattern_gen.v"
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// `include "vga_module.v"
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// `include "horizontal_counter.v"
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// `include "vertical_counter.v"
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module top #( parameter
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//pattern generator paremater
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SPEED = 300,
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//enable signal parameters
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WAIT = 1,
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WAIT_WIDTH = 2,
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//memory parameters
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ADDR_WIDTH = 17, // 19, //
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DATA_WIDTH = 12,
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DEPTH = 76_800, // 307_200,//
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//VGA parameters
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HSYNC_CLKS = 800,
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HSYNC_DISPLAY = 640,
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HSYNC_PULSE = 96,
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HSYNC_FRONT_PORCH = 16,
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HSYNC_BACK_PORCH = 48,
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VSYNC_LINES = 521,
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VSYNC_DISPLAY = 480,
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VSYNC_PULSE = 2,
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VSYNC_FRONT_PORCH = 10,
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VSYNC_BACK_PORCH = 29
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)(
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input clk,
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output [11:0] led,
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output [1:0] ledc, // led camera configuration indicator
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//VGA inputs outputs
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output [3:0] vgaRed,
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output [3:0] vgaBlue,
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output [3:0] vgaGreen,
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output Hsync,
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output Vsync,
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input [2:0] sw,
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//UART
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input RsRx, // UART RX Data
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output RsTx, // UART TX Data
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// 7 segment
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output [6:0] seg,
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output [3:0] an
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);
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//------internal wires and registers--------
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wire w_enable;
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wire pixel_clk;
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wire clk50;
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wire w_write;
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wire [ADDR_WIDTH-1:0] w_addr_wr;
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wire [DATA_WIDTH-1:0] w_data_wr;
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wire [ADDR_WIDTH-1:0] w_com_addr_wr;
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wire [DATA_WIDTH-1:0] w_com_data_wr;
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wire w_com_write;
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wire [ADDR_WIDTH-1:0] w_com_addr_rd;
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// wire [ADDR_WIDTH-1:0] w_addrb;
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wire [ADDR_WIDTH-1:0] w_addr_rd;
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wire [DATA_WIDTH-1:0] w_data_rd;
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//-----sub modules--------------------------
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clock_enable_param #(
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.WAIT(WAIT),
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.WIDTH(WAIT_WIDTH)
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) clock_enable1 (
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.clk(clk),
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.enable(w_enable)
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);
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clock_divider #(
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.DIVIDER(2),
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.WIDTH(3)
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) clk25mhz_gen (
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.clk(clk),
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.clk_out(pixel_clk)
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);
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pattern_gen #(
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.DEPTH(DEPTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.SPEED(SPEED)
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) pattern_gen1 (
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.clk(clk),
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// .sw(sw[1]),
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.i_enable(w_enable),
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.o_addr(w_addr_wr),
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.o_data(w_data_wr),
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.o_write(w_write)
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);
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rams_tdp_rf_rf #(
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.DEPTH(DEPTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH))
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bram3(
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// -------------------------PORT A
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.clka(clk),
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.ena( 1'b1 /*w_enable*/),
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.wea( w_wea_bram ),
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.addra( w_addra_bram ),
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.dia( w_dia_bram ),
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.doa( w_doa_bram ),
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//---------------------------PORT B
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.clkb(clk),
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.addrb( w_addr_rd ),
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.enb(w_enable),
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//.web(),
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//.dib(),
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.dob(w_data_rd));
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vga_module #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(DEPTH),
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.HSYNC_CLKS(HSYNC_CLKS),
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.HSYNC_DISPLAY(HSYNC_DISPLAY),
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.HSYNC_PULSE(HSYNC_PULSE),
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.HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH),
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.HSYNC_BACK_PORCH(HSYNC_BACK_PORCH),
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.VSYNC_LINES(VSYNC_LINES) ,
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.VSYNC_DISPLAY(VSYNC_DISPLAY) ,
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.VSYNC_PULSE(VSYNC_PULSE) ,
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.VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
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.VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
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) vga_module1 (
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.clk(pixel_clk),
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.o_vgaRed(vgaRed),
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.o_vgaBlue(vgaBlue),
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.o_vgaGreen(vgaGreen),
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.o_Hsync(Hsync),
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.o_Vsync(Vsync),
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.o_display(),
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.o_addr_rd(w_addr_rd),
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.o_data_rd(w_data_rd)
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);
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com_to_mem #(
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.WAIT(WAIT),
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.WAIT_WIDTH(WAIT_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(DEPTH)
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) com_to_mem1 (
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.clk(clk),
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.sw(sw[0]),
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//.i_data_rd(w_doa_bram),
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.i_enable(w_enable),
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.o_addr_wr(w_com_addr_wr),
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.o_addr_rd(w_com_addr_rd),
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.o_data_wr(w_com_data_wr),
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.o_write(w_com_write),
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.RsRx(RsRx), // UART RX Data
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.RsTx(RsTx), // UART TX Data
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.seg(seg),
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.an(an),
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.o_addr_wr_reg(w_addr_com_wr_reg),
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.o_data_reg(w_data_com_reg),
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.o_we_reg(w_we_com_reg)
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);
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// debounce_switch debounce_switch_reset(
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// .clk(clk),
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// .i_switch(btnU),
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// .o_switch(w_reset_default)
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// );
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endmodule |