imants/FPGA-Mandelbrot-Set
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Imants Pulkstenis 033bb04bf6 Add Matlab files
2019-07-22 22:06:56 +03:00
Matlab
Add Matlab files
2019-07-22 22:06:56 +03:00
7segment_tb.v
Initial file upload
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7segment.v
Initial file upload
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Basys3_Master.xdc
Writing test pattern for VGA to multiple BRAM
2019-07-18 23:32:23 +03:00
blockram.v
new MUX file, VGA memory splited in 15 seperate parts
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clock_divider_param_tb.v
Initial file upload
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clock_divider_param.v
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clock_enable_param.v
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clock_enable_tb.v
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com_to_mem_FSM_hex.v
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com_to_mem_module.v
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com_to_mem_tb.v
Initial file upload
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debounce_switch.v
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horizontal_counter.v
Initial file upload
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mux_tb.v
Writing test pattern for VGA to multiple BRAM
2019-07-18 23:32:23 +03:00
mux.v
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pattern_gen_tb.v
Initial file upload
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pattern_gen.v
Writing test pattern for VGA to multiple BRAM
2019-07-18 23:32:23 +03:00
README.md
new MUX file, VGA memory splited in 15 seperate parts
2019-07-12 16:02:57 +03:00
top_tb.v
Writing test pattern for VGA to multiple BRAM
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top.v
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UART_Loopback_module.v
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UART_Loopback_tb.v
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UART_RX.v
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UART_TX.v
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vertical_counter.v
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vga_module.v
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2019-07-22 22:06:56 +03:00

README.md

FPGA Mandelbrot Set on Digilent Basys3 Xilinx Artix 7 (Not finished)

Mandelbrot set visualization

picture

I will try make Cornell University ECE 5760: Laboratory 3 Mandelbrot set visualization. http://people.ece.cornell.edu/land/courses/ece5760/LABS/s2019/lab3_mandelbrot.html

Lectures:

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Description
Mandelbrot set visualization
Readme
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Verilog 83.3%
Tcl 13.8%
MATLAB 2.9%