47 lines
1.8 KiB
Verilog
47 lines
1.8 KiB
Verilog
// This I2S Playback design uses the common 44.1 kHz
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// sampling frequency.
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// From Figure 2 in Section 4.1.1 of the CS5343
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// Datasheet, it is appropriate to use an SCLK/LRCK
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// ratio of 64 and a MCLK/LRCK ratio of 256.
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// Therefore, the I2S Transceiver’s generic
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// parameter sclk_ws_ratio is set to 64.
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// (LRCK, e.g. left-right clock, and ws,
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// e.g. word select, are synonymous.)
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// The generic parameter mclk_sclk_ratio is set to 4,
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// since MCLK/SCLK = (MCLK/LRCK) / (SCLK/LRCK) = 256/64 = 4.
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module i2c_transceiver #( parameter
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d_width = 24 // data width
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mclk_sclk_ratio => 4,
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sclk_ws_ratio => 64
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)(
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input clock, // system clock (100 MHz on Basys board)
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input reset_n, // active low asynchronous reset
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output mclk, // master clock
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output sclk, // serial clock (or bit clock)
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output ws, // word select (or left-right clock)
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input sd_rx, // serial data in
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output sd_tx // serial data out
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);
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wire master_clk; //internal master clock signal
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reg serial_clk = 0; //internal serial clock signal
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reg word_select = 0; //internal word select signal
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wire l_data_rx[d_width-1 : 0]; //left channel data received from I2S Transceiver component
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wire r_data_rx[d_width-1 : 0]; //right channel data received from I2S Transceiver component
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wire l_data_tx[d_width-1 : 0]; //left channel data to transmit using I2S Transceiver component
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wire r_data_tx[d_width-1 : 0]; //right channel data to transmit using I2S Transceiver component
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//declare PLL to create 11.29 MHz master clock from 100 MHz system clock
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clk_wiz_0 clk_wiz_0(
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.clk_in1(clock),
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.clk_out1(master_clk)
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);
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endmodule |