81 lines
2.1 KiB
Verilog
81 lines
2.1 KiB
Verilog
// This file is Test Bench for top_vga_mem module
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//
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//
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// 100MHz clock on Basys3 -> 10ns period
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// 50% duty cycle 5ns HIGH and 5ns LOW
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//`timescale [time unit] / [time precision]
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`timescale 10 ns / 1ns
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//top module
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`include "i2s_transceiver.v"
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module i2s_transceiver_tb#( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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d_width = 24 // data width
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)();
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reg clk = 1'b0;
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reg reset_n = 0;
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reg sd_rx = 0;
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reg [d_width-1: 0] l_data_tx = 0;
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reg [d_width-1: 0] r_data_tx = 0;
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wire sclk;
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wire ws;
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wire sd_tx;
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wire [d_width-1: 0] l_data_rx;
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wire [d_width-1: 0] r_data_rx;
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// 50% duty cycle clock
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always #0.5 clk <= ~clk;
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i2s_transceiver UUT(
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.reset_n(reset_n), //asynchronous active low reset
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.mclk(clk), //master clock
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.sclk(sclk), //serial clock (or bit clock)
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.ws(ws), //word select (or left-right clock)
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.sd_tx(sd_tx), //serial data transmit
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.sd_rx(sd_rx), //serial data receive
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.l_data_tx(l_data_tx), //left channel data to transmit
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.r_data_tx(r_data_tx), //right channel data to transmit
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.l_data_rx(l_data_rx), //left channel data received
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.r_data_rx(r_data_rx) //right channel data received
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);
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initial begin
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#200
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reset_n <= 1;
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#200
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l_data_tx = 'h2563;
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r_data_tx = 'h1523;
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#20
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sd_rx = 'h1;
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end
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initial begin
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#3_000_000;
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$display("*");
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$display(" ");
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$display("Use this command to open timing diagram:");
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$display("gtkwave -f wave.vcd");
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$display("----------------------------------------------");
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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end
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endmodule |