184 lines
5.5 KiB
Verilog
184 lines
5.5 KiB
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 04.04.2020
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// Project name - Audio FFT on FPGA
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// Module name - Top module
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//
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// Detailed module description:
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//
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//
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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module top #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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d_width = 24, // data width for I2S
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memory_d_width = 16 // data width for memory (and effects). lower bits are ignored
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)(
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input clk,
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input btnC,
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output [15:0] led,
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// 7 segment display
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output [6:0] seg,
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output dp,
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output [3:0] an,
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//VGA inputs outputs
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output [3:0] vgaRed,
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output [3:0] vgaBlue,
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output [3:0] vgaGreen,
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output Hsync,
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output Vsync,
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input [15:0] sw, // swiches on board to control effects
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output da_mclk,
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output ad_mclk,
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output da_sclk,
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output ad_sclk,
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output da_lrck,
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output ad_lrck,
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input ad_sdout,
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output da_sdin,
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output [7: 0] JXADC // output for logic analizer
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);
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//assign output from effect controler to leds
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assign led = sw;
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assign da_mclk = master_clk; //output master clock to ADC
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assign ad_mclk = master_clk; //output master clock to DAC
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// assign da_sdin = w_sd_tx; //assign received data to transmit (to playback out received data)
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//------internal wires and registers--------
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wire master_clk; // 11.29 MHz master clock
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wire clk_50MHz; // 50 MHz clock
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wire clk_25MHz; // 25 MHz clock
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wire w_reset;
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wire w_internal_reset;
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// wire signed [d_width-1: 0] r_data_tx;
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// wire signed [d_width-1: 0] l_data_tx;
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wire signed [d_width-1: 0] r_data_rx;
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wire signed [d_width-1: 0] l_data_rx;
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wire [d_width-1: 0] w_data_to_eff;
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wire w_dv_to_eff;
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wire w_dv_from_eff;
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wire w_rd_en_from_eff;
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wire w_read_done_eff; // read done from effects module to mixer
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wire w_read_ready_eff; // ready to read from effects module
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// Data wires from effects module to effect controler
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wire [d_width-1: 0] w_data_from_eff_sw0;
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wire [d_width-1: 0] w_data_from_eff_sw1;
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//-----sub modules--------------------------
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// declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S
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//
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// Common clocking errors with 7-Series FPGAs
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// http://www.markharvey.info/art/7clk_19.10.2015/7clk_19.10.2015.html
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clk_wiz_0 m_clk(
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.clk_in1(clk),
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.clk_out1(master_clk), // 11.29 MHz master clock for I2S
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.clk_out2(clk_50MHz), // 50MHz main clock
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.clk_out3(clk_25MHz), // 25MHz main clock
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.locked(w_internal_reset),
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.reset(btnC)
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);
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// Flip-flop for reset
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d_flipflop_sync_rst D_flipflop1 (
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.D(1'b0),
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.Q(w_reset),
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.clk(master_clk),
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.reset(~w_internal_reset));
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io_module #(
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.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
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.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
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.d_width(d_width) //data width
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) io_module (
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.reset(reset_n), //asynchronous active high reset
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.mclk(master_clk), //master clock
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.da_sclk(da_sclk), //serial clock (or bit clock)
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.da_ws(da_lrck), //word select (or left-right clock)
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.ad_sclk(ad_sclk), //serial clock (or bit clock)
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.ad_ws(ad_lrck), //word select (or left-right clock)
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.sd_tx(da_sdin), //serial data transmit
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.sd_rx(ad_sdout), //serial data receive
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.l_data_tx(l_data_rx), //left channel data to transmit
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.r_data_tx(r_data_rx), //right channel data to transmit
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.reset(w_reset), //reset
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.l_data_rx(l_data_rx), //left channel data received
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.r_data_rx(r_data_rx), //right channel data received
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// inputs to logic analyzer
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.ch0(Hsync),
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.ch1(Vsync),
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.ch2(),
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.ch3(),
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.ch4(),
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.ch5(),
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.ch6(),
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.ch7(),
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.JXADC(JXADC) // output for logic analizer
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);
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segment4x7 segment4x7(
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.clk(clk10k), // 10kHz clock
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.in(sw), // input
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.seg(seg), // individual segments of number
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.an(an), // anode to select character
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.dp(dp) // dot on 7segment display
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);
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clock_divider #(.WIDTH(11))
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clock_divider7seg (
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.clk_in(clk_50MHz),
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.clk_out(clk10k)
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);
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vga_module #(
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// .ADDR_WIDTH(ADDR_WIDTH),
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// .DATA_WIDTH(DATA_WIDTH),
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// .DEPTH(DEPTH),
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// .HSYNC_CLKS(HSYNC_CLKS),
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// .HSYNC_DISPLAY(HSYNC_DISPLAY),
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// .HSYNC_PULSE(HSYNC_PULSE),
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// .HSYNC_FRONT_PORCH(HSYNC_FRONT_PORCH),
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// .HSYNC_BACK_PORCH(HSYNC_BACK_PORCH),
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// .VSYNC_LINES(VSYNC_LINES) ,
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// .VSYNC_DISPLAY(VSYNC_DISPLAY) ,
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// .VSYNC_PULSE(VSYNC_PULSE) ,
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// .VSYNC_FRONT_PORCH(VSYNC_FRONT_PORCH) ,
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// .VSYNC_BACK_PORCH(VSYNC_BACK_PORCH)
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) vga_module1 (
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.clk(clk_25MHz),
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.o_vgaRed(vgaRed),
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.o_vgaBlue(vgaBlue),
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.o_vgaGreen(vgaGreen),
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.o_Hsync(Hsync),
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.o_Vsync(Vsync),
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.o_display(),
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.o_addr_rd(),
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.i_data_rd()
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);
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endmodule |