62 lines
1.2 KiB
Verilog
62 lines
1.2 KiB
Verilog
// TOP module
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//
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// Fs = audio sample frequency
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// I2S bitrate = (#bits/channel) x (#channels) x Fs
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// Ex: 24-bit stereo (2 channels)
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// I2S bitrate = 24 x 2 x Fs
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//
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// I2SxCLK source = PLLI2S output or ext. input (I2S_CKIN)
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// Fs = 48kHz, 96kHz or 192kHz
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// Fs = I2SxCLK / [(CF*2) * (2*I2SDIV+ODD)*8)]
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// CF = channel frame (24 bits)
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//
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// `include "clock_divider_param.v"
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// `include "clock_enable_param.v"
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// `include "debounce_switch.v"
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module top #( parameter
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//enable signal parameters
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WAIT = 1,
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WAIT_WIDTH = 2
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)(
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input clk
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);
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//------internal wires and registers--------
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// wire w_enable;
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wire clk48k;
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wire clk25M;
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//-----sub modules--------------------------
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// clock_enable_param #(
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// .WAIT(WAIT),
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// .WIDTH(WAIT_WIDTH)
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// ) clock_enable1 (
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// .clk(clk),
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// .enable(w_enable)
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// );
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clock_divider #(
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.DIVIDER(1042),
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.WIDTH(11)
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) clk48k_gen (
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.clk(clk),
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.clk_out(clk48k) // 48kHz clock
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);
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clock_divider #(
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.DIVIDER(2),
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.WIDTH(2)
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) clk25M_gen (
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.clk(clk),
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.clk_out(clk25M) // 25MHz clock
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);
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// debounce_switch debounce_switch_reset(
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// .clk(clk),
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// .i_switch(),
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// .o_switch()
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// );
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endmodule |