42 lines
1.1 KiB
Verilog
42 lines
1.1 KiB
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 04.04.2020
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// Project name - Audio FFT on FPGA
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// Module name - Debounce switch
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//
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// Detailed module description:
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// This is Debounce switch module.
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// It toggles output only when input is in
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// HIGH or LOW state atleast for 10ms
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////module debounce_switch(
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input clk,
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input i_switch,
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output o_switch);
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// parameter c_debounce_limit=250000;// 2.5ms at 25MHz
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// parameter c_debounce_limit=1_000_000;// 10ms at 100MHz
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parameter c_debounce_limit=100_000; // 10ms at 10MHz
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reg r_state=1'b0;
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reg [19:0] r_count = 0;
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always@(posedge clk)begin
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if (i_switch != r_state && r_count < c_debounce_limit)
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r_count <= r_count +1; //counter
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else if (r_count == c_debounce_limit)begin
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r_count <=0;
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r_state <= i_switch;
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end
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else
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r_count<=0;
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end
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assign o_switch=r_state;
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endmodule |