34 lines
841 B
Verilog
34 lines
841 B
Verilog
/////////////////////////////////////////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 04.04.2020
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// Project name - Audio FFT on FPGA
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// Module name - JXADC PMOD connector output
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//
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// Detailed module description:
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// This module outputs signals to JXADC PMOD
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// where logic analyzer are conected.
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// Port is connected to logic analizer
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//
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// Revision:
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// A - initial design
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// B -
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// C -
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//
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///////////////////////////////////////////////////////////////////
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module JXADC_controler (
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input ch0,
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input ch1,
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input ch2,
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input ch3,
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input ch4,
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input ch5,
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input ch6,
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input ch7,
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output [7: 0] JXADC // output for logic analizer
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);
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assign JXADC = {ch7,ch6,ch5,ch4,ch3,ch2,ch1,ch0};
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endmodule |