68 lines
1.9 KiB
Verilog
68 lines
1.9 KiB
Verilog
module effect_controler #( parameter
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d_width = 24, // data width
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address_width = 4, //
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ram_depth = 16, //
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memory_d_width = 16 //
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)(
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input clk,
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input reset,
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input signed [d_width-1: 0] i_l_data,
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input signed [d_width-1: 0] i_r_data, // not used
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output signed [d_width-1: 0] o_l_data,
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output signed [d_width-1: 0] o_r_data
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);
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wire signed [memory_d_width: 0] w_o_data;
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wire w_empty, w_full;
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wire [address_width:0] w_data_fill;
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assign o_l_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // only left chanal are used in controler
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assign o_r_data [ d_width-1 : d_width - memory_d_width ] = w_o_data; // same as left
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sync_fifo #(
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.ram_depth(ram_depth), // ram memory depth
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.address_width(address_width), // ram memory address width
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//.data_width(d_width) // data width
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.data_width(memory_d_width) // memory data width
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) fifo_l (
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.data_out(w_o_data),
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.full(w_full),
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.empty(w_empty),
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.data_fill(w_data_fill),
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.data_in(i_l_data[ d_width-1 : d_width-memory_d_width ]),
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.clk(clk),
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.rst_a(reset),
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.wr_en( w_full ? 1'b0 : 1'b1 ),
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.rd_en((w_empty & (w_data_fill > 1 )) ? 1'b0 : 1'b1)
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);
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// sync_fifo #(
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// .ram_depth(ram_depth), // ram memory depth
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// .address_width(address_width), // ram memory address width
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// .data_width(d_width) // data width
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// ) fifo_r (
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// .data_out(o_r_data),
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// .full(),
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// .empty(),
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// .data_in(i_r_data),
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// .clk(clk),
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// .rst_a(reset),
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// .wr_en(1'b1),
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// .rd_en(1'b1)
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// );
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// always@* begin
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// o_l_data <= i_l_data;
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// o_r_data <= i_r_data;
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// end
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//assign o_l_data = i_l_data;
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//assign o_r_data = i_r_data;
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//assign o_l_data = 24'h000000;
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//assign o_r_data = 24'h400008;
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endmodule |