16 lines
362 B
Verilog
16 lines
362 B
Verilog
module eclipping_effect #( parameter
|
|
data_width = 16 // data width
|
|
)(
|
|
input clk,
|
|
input reset,
|
|
input signed [data_width-1: 0] i_data,
|
|
output signed [data_width-1: 0] o_data,
|
|
input [data_width-1: 0] i_treshhold
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
endmodule |