120 lines
3.3 KiB
Verilog
120 lines
3.3 KiB
Verilog
// Fifo code source:
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// https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
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//
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module sync_fifo #( parameter
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//---------------parametre declaration
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data_width = 4,
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address_width = 4,
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ram_depth = 16 // must be 2^n
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)(
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//--------------input output port declaration
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output reg signed [data_width-1:0] data_out,
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output full,
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output empty,
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output [address_width-1:0] data_fill,
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input signed [data_width-1:0] data_in,
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input w_clk, // write clock
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input r_clk, // read clock
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input reset,
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input wr_en,
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input rd_en);
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//--------------internal register declaration
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reg [address_width-1:0] wr_pointer = 0;
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reg [address_width-1:0] rd_pointer = 0;
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// reg [address_width :0] status_count = 0;
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wire signed [data_width-1:0] data_ram ;
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// reg addition = 0;
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// reg subtractor = 0;
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// always@(posedge addition )
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// begin
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// if (addition ^ subtractor) // if XOR
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// begin
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// if (status_count != 0)
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// status_count = status_count + 1;
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// end
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// addition = 0; // reset addition
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// end
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// always@(posedge subtractor)
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// begin
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// if (addition ^ subtractor) // if XOR
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// begin
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// if (status_count != 0)
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// status_count = status_count - 1;
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// end
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// subtractor = 0; // reset subtractor
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// end
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//--------------wr_pointer pointing to write address
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always @ (posedge w_clk,posedge reset)
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begin
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if(reset)
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wr_pointer = 0;
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else if(wr_en)
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wr_pointer = wr_pointer+1;
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//addition = 1;
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end
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//-------------rd_pointer points to read address
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always @ (posedge r_clk,posedge reset)
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begin
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if(reset)
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rd_pointer = 0;
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else if(rd_en)
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rd_pointer = rd_pointer + 1;
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//subtractor = 1;
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end
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//-------------read from FIFO
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always @ (posedge r_clk,posedge reset)
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begin
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if(reset)
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data_out=0;
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else if(rd_en)
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data_out=data_ram;
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end
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// //--------------Status pointer for full and empty checking
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// always @ (posedge w_clk,posedge r_clk,posedge reset)
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// begin
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// if(reset)
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// status_count = 0;
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// else if(wr_en && !rd_en && (status_count != ram_depth))
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// status_count = status_count + 1;
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// else if(rd_en && !wr_en && (status_count != 0))
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// status_count = status_count - 1;
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// end // always @ (posedge clk,posedge reset)
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// assign full = (status_count == (ram_depth));
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// assign empty = (status_count == 0);
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// assign data_fill = status_count; // how full are FIFO
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assign full = (wr_pointer - rd_pointer == ram_depth) ? 1'b1 : 1'b0 ;
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assign empty = (wr_pointer - rd_pointer == 0) ? 1'b1 : 1'b0 ;
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assign data_fill = wr_pointer - rd_pointer ; // how full are FIFO
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rams_tdp_rf_rf #(
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.DEPTH(ram_depth),
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.ADDR_WIDTH(address_width),
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.DATA_WIDTH(data_width)
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) memory1 (
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.addra(wr_pointer),
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.addrb(rd_pointer),
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.dia(data_in),
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.dib(),
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.doa(),
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.dob(data_ram),
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.wea(wr_en),
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.web(1'b0),
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.ena(1'b1),
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.enb(rd_en),
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.clka(w_clk),
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.clkb(r_clk)
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);
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endmodule // sync_fifo
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