93 lines
4.5 KiB
Verilog
93 lines
4.5 KiB
Verilog
// This I2S design uses the common 44.1 kHz
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// sampling frequency.
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// From Figure 2 in Section 4.1.1 of the CS5343
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// Datasheet, it is appropriate to use an SCLK/LRCK
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// ratio of 64 and a MCLK/LRCK ratio of 256.
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// Therefore, the I2S Transceiver’s generic
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// parameter sclk_ws_ratio is set to 64.
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// (LRCK, e.g. left-right clock, and ws,
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// e.g. word select, are synonymous.)
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// The generic parameter mclk_sclk_ratio is set to 4,
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// since MCLK/SCLK = (MCLK/LRCK) / (SCLK/LRCK) = 256/64 = 4.
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//
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// As such, the word select (or left-right clock) frequency
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// is 44.1 kHz, the serial clock frequency is 44.1 kHz * 64 = 2.82 MHz,
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// and the master clock frequency is 2.82 MHz * 4 = 11.29 MHz.
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// Table 1, Section 4.1 of the CS4344 Datasheet confirms this
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// selection, listing 11.29 MHz as a common frequency
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// for the master clock when the LRCK is 44.1 kHz.
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//
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// Module is created from sample provided by
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// Digilent
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//
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module i2s_receicer #( parameter
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sclk_ws_ratio = 64, // number of sclk periods per word select period
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mclk_sclk_ratio = 4, // number of mclk periods per sclk period
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d_width = 24 // data width
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)(
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input reset_n, //asynchronous active low reset
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input mclk, //master clock
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output sclk, //serial clock (or bit clock)
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output ws, //word select (or left-right clock)
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input sd_rx, //serial data receive
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output reg signed [d_width-1: 0] l_data_rx, //left channel data received
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output reg signed [d_width-1: 0] r_data_rx //right channel data received
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);
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reg sclk_int = 0; //internal serial clock wire
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reg ws_int = 0; //internal word select wire
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reg signed [d_width-1: 0] l_data_rx_int = 'sb0; //internal left channel rx data buffer
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reg signed [d_width-1: 0] r_data_rx_int = 'sb0; //internal right channel rx data buffer
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reg [3: 0] sclk_cnt = 0; //counter of master clocks during half period of serial clock
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reg [7: 0] ws_cnt = 0; //counter of serial clock toggles during half period of word select
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always@(posedge mclk, posedge reset_n) begin
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if (reset_n == 1) begin
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sclk_cnt <= 'b0; //clear mclk/sclk counter
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ws_cnt <= 'b0; //clear sclk/ws counter
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sclk_int <= 0; //clear serial clock signal
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ws_int <= 0; //clear word select signal
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l_data_rx_int <= 'sb0; //clear internal left channel rx data buffer
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r_data_rx_int <= 'sb0; //clear internal right channel rx data buffer
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end
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else begin //master clock rising edge
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if (sclk_cnt < mclk_sclk_ratio/2-1) begin //less than half period of sclk
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sclk_cnt <= sclk_cnt + 1; //increment mclk/sclk counter
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end
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else begin //half period of sclk
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sclk_cnt <= 0; //reset mclk/sclk counter
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sclk_int <= ~sclk_int; //toggle serial clock
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if (ws_cnt < sclk_ws_ratio - 1) begin //less than half period of ws
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ws_cnt <= ws_cnt + 1; //increment sclk/ws counter
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if (sclk_int == 0 && ws_cnt > 1 && ws_cnt < d_width * 2 + 2) begin //rising edge of sclk during data word
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if (ws_int == 1) begin //right channel
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r_data_rx_int <= {r_data_rx_int[d_width-2 : 0] , sd_rx}; //shift data bit into right channel rx data buffer
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end else begin //left channel
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l_data_rx_int <= {l_data_rx_int[d_width-2 : 0] , sd_rx}; //shift data bit into left channel rx data buffer
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end
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end
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end else begin //half period of ws
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ws_cnt <= 0; //reset sclk/ws counter
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ws_int <= ~ws_int; //toggle word select
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r_data_rx <= r_data_rx_int; //output right channel received data
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l_data_rx <= l_data_rx_int; //output left channel received data
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end
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end
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end
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end
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assign sclk = sclk_int; //output serial clock
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assign ws = ws_int; //output word select
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endmodule |