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Clipping effect now working

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Imants Pulkstenis
2019-11-24 01:43:20 +02:00
parent 45caf399a1
commit edf1ece511
4 changed files with 132 additions and 35 deletions
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Basys3_Master.xdc
+4 -4
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@@ -14,10 +14,10 @@ set_property PACKAGE_PIN W5 [get_ports clk]
## Switches ## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}] set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}] set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}] #set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}] #set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
clipping.v
+84 -2
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@@ -1,15 +1,97 @@
module eclipping_effect #( parameter module clipping_effect #( parameter
data_width = 16 // data width data_width = 16 // data width
)( )(
input clk, input clk,
input reset, input reset,
input signed [data_width-1: 0] i_data, input signed [data_width-1: 0] i_data,
output signed [data_width-1: 0] o_data, output signed [data_width-1: 0] o_data,
input [data_width-1: 0] i_treshhold input signed [data_width-1: 0] i_treshhold,
input i_read_done,
output o_read_enable,
output o_data_valid,
input i_data_ready
); );
//-------------Internal Constants---------------------------
localparam [3:0] IDLE = 'd0,
CLIP = 'd1,
OUTPUT = 'd2;
reg [3:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0;
reg signed [data_width-1: 0] r_treshhold_p = 'b0;
reg signed [data_width-1: 0] r_treshhold_n = 'b0;
reg r_read_enable = 0;
reg r_data_valid = 0;
assign o_read_enable = r_read_enable;
assign o_data_valid = r_data_valid;
assign o_data = r_data;
//---------state register sequential always block-----------
always @(posedge clk ) begin
if (reset == 1) begin
// clear state
r_state <= IDLE;
r_next <= IDLE;
end
else begin
r_state <= r_next;
end
end
//----next state & outputs, combinational always block------
always @(posedge clk ) begin
case(r_state)
IDLE : begin
if (i_data_ready == 1) begin
r_next <= CLIP;
r_data <= i_data;
r_treshhold_p <= i_treshhold;
r_treshhold_n <= 0 - i_treshhold;
r_read_enable <= 0;
r_data_valid <= 0;
end
else begin
r_next <= IDLE;
r_read_enable <= 1; // redy to read data
r_data_valid <= 0;
end
end
CLIP : begin
case (r_data < 0 )
0 : begin // positive number
if (r_data > r_treshhold_p)
r_data <= r_treshhold_p;
end
1 : begin // negative number
if (r_data < r_treshhold_n)
r_data <= r_treshhold_n;
end
endcase
r_next <= OUTPUT;
r_data_valid <= 0;
r_read_enable <= 0; // read disable
end
OUTPUT : begin
if (i_read_done == 1) begin
r_next <= IDLE;
r_data_valid <= 0;
r_read_enable <= 1;
end
else begin
r_next <= OUTPUT;
r_data_valid <= 1;
r_read_enable <= 0; // read disable
end
end
default: r_next <= IDLE; // on error
endcase
end
effect_module.v
+28 -15
View File
@@ -3,28 +3,41 @@ module effect_module #( parameter
)( )(
input clk, input clk,
input reset, input reset,
input [1:0] sw, // effect control swiches
input i_data_ready, // data ready to read input i_data_ready, // data ready to read
input signed [d_width-1: 0] i_data, // data input form effect controler input signed [d_width-1: 0] i_data, // data input form effect controler
output read_enable, // enable data reading output o_read_enable, // enable data reading
input i_read_done, // read done from effects controler
output signed [d_width-1: 0] o_data, // data output form effect controler output signed [d_width-1: 0] o_data, // data output form effect controler
output o_data_valid
output data_valid
); );
assign o_data = i_data_ready ? i_data : 'b0 ; // Wires for cliping effect
assign read_enable = i_data_ready ? 1 : 0 ; wire signed [d_width-1: 0] w_data_ce;
assign data_valid = i_data_ready ? 1 : 0 ; wire w_read_enable_ce;
wire w_data_valid_ce;
// // cliping effect
// eclipping_effect #( assign o_data = w_data_ce;// ? w_data_ce : 'b0 ;
// .data_width(d_width) // data width assign o_read_enable = w_read_enable_ce;//(i_data_ready & w_data_valid_ce ) ? w_read_enable_ce : 0 ;
// ) eclipping_effect ( assign o_data_valid = w_data_valid_ce;//(i_data_ready & w_data_valid_ce ) ? w_data_valid_ce : 0 ;
// .clk(clk),
// .reset(reset),
// .i_data(i_data), // clipping effect
// .o_data(o_data) clipping_effect #(
// ); .data_width(d_width) // data width
) clipping_effect (
.clk(clk),
.reset(reset),
.i_treshhold(16'h00f0),
.i_data(i_data),
.i_read_done(i_data_ready),
.o_data(w_data_ce),
.o_read_enable(w_read_enable_ce),
.o_data_valid(w_data_valid_ce),
.i_data_ready(i_data_ready)
);
endmodule endmodule
top.v
+12 -10
View File
@@ -11,6 +11,7 @@ module top #( parameter
)( )(
input clk, input clk,
input btnC, input btnC,
input [1:0] sw, // swiches on board to control effects
output da_mclk, output da_mclk,
output ad_mclk, output ad_mclk,
output da_sclk, output da_sclk,
@@ -94,21 +95,21 @@ io_module #(
//Effect controler controls effects and perfoms multiplexing and data marging //Effect controler controls effects and perfoms multiplexing and data marging
effect_controler #( effect_controler #(
.d_width(d_width), //data width .d_width(d_width), // data width
.memory_d_width(memory_d_width) .memory_d_width(memory_d_width)
) effect_controler ( ) effect_controler (
.reset(reset_n), //asynchronous active high reset .reset(reset_n), // asynchronous active high reset
.mclk(master_clk), .mclk(master_clk),
.clk(clk_25MHz), .clk(clk_25MHz),
.i_l_data(l_data_rx), //left channel data received .i_l_data(l_data_rx), // left channel data received
.i_r_data(r_data_rx), //right channel data received .i_r_data(r_data_rx), // right channel data received
.o_l_data(l_data_tx), //left channel data to transmit .o_l_data(l_data_tx), // left channel data to transmit
.o_r_data(r_data_tx), //right channel data to transmit .o_r_data(r_data_tx), // right channel data to transmit
.o_data_to_eff(w_data_to_eff), // Data output to effects module .o_data_to_eff(w_data_to_eff), // Data output to effects module
.o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module .o_data_valid(w_dv_to_eff), // data valid to read (FIFO not empty). data valid signal to effect module
.i_read_enable(w_rd_en_from_eff), //read enable from Effect module .i_read_enable(w_rd_en_from_eff), // read enable from Effect module
.i_data_from_eff(w_data_from_eff), // Data input from effects module .i_data_from_eff(w_data_from_eff), // Data input from effects module
.i_dv_from_eff(w_dv_from_eff) // data valid write (FIFO not full). data valid signal from effect module .i_dv_from_eff(w_dv_from_eff) // data valid write (FIFO not full). data valid signal from effect module
); );
@@ -116,15 +117,16 @@ effect_controler #(
//Effect module contains all individual effects //Effect module contains all individual effects
effect_module #( effect_module #(
.d_width(memory_d_width) //data width .d_width(memory_d_width) // data width
) effect_module ( ) effect_module (
.clk(clk_25MHz), .clk(clk_25MHz),
.reset(reset_n), .reset(reset_n),
.sw(sw), // effect control swiches
.i_data_ready(w_dv_to_eff), // data ready to read .i_data_ready(w_dv_to_eff), // data ready to read
.i_data(w_data_to_eff), // data input form effect controler .i_data(w_data_to_eff), // data input form effect controler
.read_enable(w_rd_en_from_eff), // enable data reading .o_read_enable(w_rd_en_from_eff), // enable data reading
.o_data(w_data_from_eff), .o_data(w_data_from_eff),
.data_valid(w_dv_from_eff) .o_data_valid(w_dv_from_eff)
); );