add fifo memory block

blockram.v

@@ -0,0 +1,40 @@
+// Code from:
+// Vivado Design Suite
+// User Guide
+// Synthesis
+// UG901 (v2018.3) December 19, 2018
+//
+// Dual-Port Block RAM with Two Write Ports
+// File: blobkram.v
+
+module ram #( parameter
+    DEPTH =  16,
+    ADDR_WIDTH = 4, 
+    DATA_WIDTH = 24 ) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
+
+input                       clka,clkb,ena,enb,wea,web;
+input   [ADDR_WIDTH-1:0]    addra,addrb;
+input   [DATA_WIDTH-1:0]    dia,dib;
+output  [DATA_WIDTH-1:0]    doa,dob;
+reg     [ADDR_WIDTH-1:0]    ram     [ DEPTH - 1 :0];
+reg     [DATA_WIDTH-1:0]    doa,dob;
+
+always @(posedge clka)
+begin
+    if (ena)
+    begin
+        if (wea)
+            ram[addra] <= dia;
+            doa <= ram[addra];
+        end
+    end
+always @(posedge clkb)
+begin
+    if (enb)
+    begin
+        if (web)
+            ram[addrb] <= dib;
+            dob <= ram[addrb];
+    end
+end
+endmodule

effect_controler.v

@@ -1,17 +1,53 @@
 module effect_controler #( parameter
-    d_width = 24                // data width
+    d_width = 24,                // data width
+    address_width = 4,           // 
+    ram_depth = 16                // 
 )(
-//    input clk,
+    input                               clk,
-    input signed [d_width-1: 0] i_l_data,
+    input                               reset,
-    input signed  [d_width-1: 0] i_r_data,
+    input   signed      [d_width-1: 0]  i_l_data,
-    output reg signed [d_width-1: 0] o_l_data,
+    input   signed      [d_width-1: 0]  i_r_data,
-    output  reg signed [d_width-1: 0] o_r_data
+    output   signed  [d_width-1: 0]  o_l_data,
+    output   signed  [d_width-1: 0]  o_r_data
 );
 
-always@* begin
+
-    o_l_data <= i_l_data;
+
-    o_r_data <= i_r_data;
+sync_fifo #( 
-end
+   .ram_depth(ram_depth),               // ram memory depth
+   .address_width(address_width),       // ram memory address width
+   .data_width(d_width)                 // data width
+) fifo_l (
+   .data_out(o_l_data),
+   .full(),
+   .empty(),
+   .data_in(i_l_data),
+   .clk(clk),
+   .rst_a(reset),
+   .wr_en(1'b1),
+   .rd_en(1'b1)
+);
+
+sync_fifo #( 
+   .ram_depth(ram_depth),               // ram memory depth
+   .address_width(address_width),       // ram memory address width
+   .data_width(d_width)                 // data width
+) fifo_r (
+   .data_out(o_r_data),
+   .full(),
+   .empty(),
+   .data_in(i_r_data),
+   .clk(clk),
+   .rst_a(reset),
+   .wr_en(1'b1),
+   .rd_en(1'b1)
+);
+
+
+// always@* begin
+//     o_l_data <= i_l_data;
+//     o_r_data <= i_r_data;
+// end
 
 //assign o_l_data = i_l_data;
 //assign o_r_data = i_r_data;

sync_fifo.v

@@ -0,0 +1,90 @@
+// Fifo code source:
+// https://vlsicoding.blogspot.com/2013/11/verilog-code-for-synchronous-fifo.html
+// 
+module sync_fifo #(
+//---------------parametre declaration
+   parameter    data_width       = 4,
+   parameter    address_width    = 4,
+   parameter    ram_depth        = 16 
+)(
+//--------------input output port declaration
+   output reg  [data_width-1:0]  data_out,
+   output                        full,
+   output                        empty,
+   input       [data_width-1:0]  data_in,
+   input                         clk,
+   input                         rst_a,
+   input                         wr_en,
+   input                         rd_en);
+ 
+
+//--------------internal register declaration
+reg      [address_width-1:0]     wr_pointer;
+reg      [address_width-1:0]     rd_pointer;
+reg      [address_width :0]      status_count;
+reg      [data_width-1:0]        data_out ;
+wire     [data_width-1:0]        data_ram ;
+
+
+ 
+//--------------wr_pointer pointing to write address
+   always @ (posedge clk,posedge rst_a)
+   begin
+      if(rst_a)
+         wr_pointer = 0;
+      else if(wr_en)
+         wr_pointer = wr_pointer+1;
+   end
+//-------------rd_pointer points to read address
+   always @ (posedge clk,posedge rst_a)
+   begin
+      if(rst_a)
+         rd_pointer = 0;
+      else if(rd_en)
+         rd_pointer = rd_pointer+1;
+   end
+//-------------read from FIFO
+   always @ (posedge clk,posedge rst_a)
+   begin
+      if(rst_a)
+         data_out=0;
+      else if(rd_en)
+         data_out=data_ram;
+   end
+
+//--------------Status pointer for full and empty checking
+   always @ (posedge clk,posedge rst_a)
+   begin
+      if(rst_a)
+         status_count = 0;
+      else if(wr_en && !rd_en && (status_count != ram_depth))
+         status_count = status_count + 1;
+      else if(rd_en && !wr_en && (status_count != 0))
+         status_count = status_count - 1;
+   end // always @ (posedge clk,posedge rst_a)
+
+
+assign full = (status_count == (ram_depth));
+assign empty = (status_count == 0);
+ 
+ram #( 
+   .DEPTH(ram_depth),
+   .ADDR_WIDTH(address_width),
+   .DATA_WIDTH(data_width)
+) memory1 (
+   .addra(wr_pointer),
+   .addrb(rd_pointer),
+   .dia(data_in),
+   .dib(),
+   .doa(),
+   .dob(data_ram),
+   .wea(wr_en),
+   .web(1'b0),
+   .ena(1'b1),
+   .enb(rd_en),
+   .clka(clk),
+   .clkb(clk)
+);
+
+endmodule // sync_fifo
+

top.v

@@ -106,7 +106,8 @@ i2s_receicer  #(
 effect_controler #(
     .d_width(d_width)                       //data width
 ) effect_controler (
-//  .clk(clk),
+    .reset(reset_n),                    //asynchronous active high reset
+    .clk(master_clk),
     .i_l_data(l_data_rx),               //left channel data received         
     .i_r_data(r_data_rx),               //right channel data received
     .o_l_data(l_data_tx),               //left channel data to transmit