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Main clk speed changed from 25MHz to 50MHz

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add LEDs (outputs data from effects controler)
add switches to control cliping treshold
This commit is contained in:
Imants Pulkstenis
2019-12-03 22:41:14 +02:00
parent c86c2a267b
commit 9701ead6d3
4 changed files with 87 additions and 78 deletions
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Basys3_Master.xdc
+61 -61
View File
@@ -18,69 +18,69 @@ set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}] set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}] set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}] set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}] set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}] set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}] set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}] set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}] set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}] set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}] set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}] set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}] set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}] set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}] set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}] set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs # LEDs
#set_property PACKAGE_PIN U16 [get_ports {led[0]}] set_property PACKAGE_PIN U16 [get_ports {led[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#set_property PACKAGE_PIN E19 [get_ports {led[1]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
#set_property PACKAGE_PIN U19 [get_ports {led[2]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
#set_property PACKAGE_PIN V19 [get_ports {led[3]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}] set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}] set_property PACKAGE_PIN V3 [get_ports {led[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}] set_property PACKAGE_PIN W3 [get_ports {led[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}] set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}] set_property PACKAGE_PIN P3 [get_ports {led[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}] set_property PACKAGE_PIN N3 [get_ports {led[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}] set_property PACKAGE_PIN P1 [get_ports {led[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}] set_property PACKAGE_PIN L1 [get_ports {led[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display ##7 segment display
clipping.v
+4 -4
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@@ -20,8 +20,8 @@ localparam [2:0] IDLE = 'd0,
reg [2:0] r_state=IDLE, r_next=IDLE; reg [2:0] r_state=IDLE, r_next=IDLE;
reg signed [data_width-1: 0] r_data = 'b0; reg signed [data_width-1: 0] r_data = 'b0;
reg signed [data_width-1: 0] r_treshhold_p = 'b0; reg [data_width-1: 0] r_treshhold_p = 'b0;
reg signed [data_width-1: 0] r_treshhold_n = 'b0; reg [data_width-1: 0] r_treshhold_n = 'b0;
reg r_read_enable = 0; reg r_read_enable = 0;
reg r_data_valid = 0; reg r_data_valid = 0;
@@ -52,7 +52,7 @@ always @(posedge clk ) begin
r_next <= CLIP; r_next <= CLIP;
r_data <= i_data; r_data <= i_data;
r_treshhold_p <= i_treshhold; r_treshhold_p <= i_treshhold;
r_treshhold_n <= 0 - i_treshhold; r_treshhold_n <= (~i_treshhold) + 1; // two compliment
r_read_enable <= 0; r_read_enable <= 0;
r_data_valid <= 0; r_data_valid <= 0;
end end
@@ -63,7 +63,7 @@ always @(posedge clk ) begin
end end
end end
CLIP : begin CLIP : begin
case (r_data < 0 ) case (r_data[data_width-1])
0 : begin // positive number 0 : begin // positive number
if (r_data > r_treshhold_p) if (r_data > r_treshhold_p)
r_data <= r_treshhold_p; r_data <= r_treshhold_p;
effect_module.v
+3 -2
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@@ -3,7 +3,8 @@ module effect_module #( parameter
)( )(
input clk, input clk,
input reset, input reset,
input [1:0] sw, // effect control swiches input [1:0] sw, // effect control switches
input [13:0] i_treshhold, // treshhold from switches
input i_data_ready, // data ready to read input i_data_ready, // data ready to read
input signed [d_width-1: 0] i_data, // data input form effect controler input signed [d_width-1: 0] i_data, // data input form effect controler
input i_read_done, // read done from effects controler input i_read_done, // read done from effects controler
@@ -59,7 +60,7 @@ clipping_effect #(
) clipping_effect ( ) clipping_effect (
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.i_treshhold(16'h00f0), .i_treshhold( {i_treshhold, 2'b00} ),
.i_data(i_data), .i_data(i_data),
.i_read_done(i_read_done), // read done from effects controler .i_read_done(i_read_done), // read done from effects controler
.i_data_ready(i_data_ready), .i_data_ready(i_data_ready),
top.v
+19 -11
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@@ -11,7 +11,9 @@ module top #( parameter
)( )(
input clk, input clk,
input btnC, input btnC,
input [1:0] sw, // swiches on board to control effects output [15:0] led,
// input [1:0] sw, // swiches on board to control effects
input [15:0] sw, // swiches on board to control effects
output da_mclk, output da_mclk,
output ad_mclk, output ad_mclk,
output da_sclk, output da_sclk,
@@ -23,6 +25,9 @@ module top #( parameter
output [7: 0] JXADC // output for logic analizer output [7: 0] JXADC // output for logic analizer
); );
//assign output from effect controler to leds
assign led = l_data_tx[d_width-1: d_width-16];
assign da_mclk = master_clk; //output master clock to ADC assign da_mclk = master_clk; //output master clock to ADC
assign ad_mclk = master_clk; //output master clock to DAC assign ad_mclk = master_clk; //output master clock to DAC
// assign da_sdin = w_sd_tx; //assign received data to transmit (to playback out received data) // assign da_sdin = w_sd_tx; //assign received data to transmit (to playback out received data)
@@ -31,16 +36,16 @@ assign ad_mclk = master_clk; //output master clock to DAC
//------internal wires and registers-------- //------internal wires and registers--------
wire master_clk; // 11.29 MHz master clock wire master_clk; // 11.29 MHz master clock
wire clk_25MHz; // wire clk_50MHz; //
wire w_reset, w_reset1, w_reset2, w_reset3, wire w_reset, w_reset1, w_reset2, w_reset3,
w_reset4, w_reset5; w_reset4, w_reset5;
wire w_internal_reset; wire w_internal_reset;
wire [d_width-1: 0] r_data_tx; wire signed [d_width-1: 0] r_data_tx;
wire [d_width-1: 0] l_data_tx; wire signed [d_width-1: 0] l_data_tx;
wire [d_width-1: 0] r_data_rx; wire signed [d_width-1: 0] r_data_rx;
wire [d_width-1: 0] l_data_rx; wire signed [d_width-1: 0] l_data_rx;
wire [d_width-1: 0] w_data_to_eff; wire [d_width-1: 0] w_data_to_eff;
@@ -67,7 +72,7 @@ wire [d_width-1: 0] w_data_from_eff_sw1;
clk_wiz_0 m_clk( clk_wiz_0 m_clk(
.clk_in1(clk), .clk_in1(clk),
.clk_out1(master_clk), // 11.29 MHz master clock for I2S .clk_out1(master_clk), // 11.29 MHz master clock for I2S
.clk_out2(clk_25MHz), // 25MHz main clock .clk_out2(clk_50MHz), // 25MHz main clock
.locked(w_internal_reset), .locked(w_internal_reset),
.reset(btnC) .reset(btnC)
); );
@@ -136,10 +141,12 @@ effect_controler #(
) effect_controler ( ) effect_controler (
.reset(w_reset), // asynchronous active high reset .reset(w_reset), // asynchronous active high reset
.mclk(master_clk), .mclk(master_clk),
.sw(sw), .sw(sw[1:0]),
.clk(clk_25MHz), .clk(clk_50MHz),
.i_l_data(l_data_rx), // left channel data received .i_l_data(l_data_rx), // left channel data received
.i_r_data(r_data_rx), // right channel data received .i_r_data(r_data_rx), // right channel data received
// .i_l_data({sw[15:2], 10'b0 }), // left channel data received
// .i_r_data({sw[15:2], 10'b0 }), // right channel data received
.o_l_data(l_data_tx), // left channel data to transmit .o_l_data(l_data_tx), // left channel data to transmit
.o_r_data(r_data_tx), // right channel data to transmit .o_r_data(r_data_tx), // right channel data to transmit
.o_read_done(w_read_done_eff), // read done from effects controler .o_read_done(w_read_done_eff), // read done from effects controler
@@ -159,9 +166,10 @@ effect_controler #(
effect_module #( effect_module #(
.d_width(memory_d_width) // data width .d_width(memory_d_width) // data width
) effect_module ( ) effect_module (
.clk(clk_25MHz), .clk(clk_50MHz),
.reset(w_reset), .reset(w_reset),
.sw(sw), // effect control swiches .sw(sw[1:0]), // effect control swiches
.i_treshhold(sw[15:2]),
.i_data_ready(w_dv_to_eff), // data ready to read .i_data_ready(w_dv_to_eff), // data ready to read
.i_read_done(w_read_done_eff), // read done from effects controler .i_read_done(w_read_done_eff), // read done from effects controler
.i_data(w_data_to_eff), // data input form effect controler .i_data(w_data_to_eff), // data input form effect controler