add i2s files

top.v

@@ -1,5 +1,14 @@
 //      TOP module 
 //       
+// Fs = audio sample frequency
+// I2S bitrate = (#bits/channel) x (#channels) x Fs
+//         Ex: 24-bit stereo (2 channels)
+//         I2S bitrate = 24 x 2 x Fs
+//
+// I2SxCLK source = PLLI2S output or ext. input (I2S_CKIN)
+// Fs = 48kHz, 96kHz or 192kHz
+// Fs = I2SxCLK / [(CF*2) * (2*I2SDIV+ODD)*8)]
+//         CF = channel frame (24 bits)
 //      
 // `include "clock_divider_param.v"
 // `include "clock_enable_param.v"
@@ -16,7 +25,8 @@ module top #( parameter
 
 //------internal wires and registers--------
 // wire w_enable;
-wire clk50;    
+wire clk48k;    
+wire clk25M; 
 
 //-----sub modules--------------------------
 // clock_enable_param #(
@@ -28,11 +38,19 @@ wire clk50;
 // );
 
 clock_divider #(
-    .DIVIDER(1),
-    .WIDTH(3)
-) clk50mhz_gen (
+    .DIVIDER(1042),
+    .WIDTH(11)
+) clk48k_gen (
     .clk(clk),
-    .clk_out(clk50)
+    .clk_out(clk48k) // 48kHz clock 
+);
+
+clock_divider #(
+    .DIVIDER(2),
+    .WIDTH(2)
+) clk25M_gen (
+    .clk(clk),
+    .clk_out(clk25M) // 25MHz clock 
 );
 
 // debounce_switch debounce_switch_reset(