repaired i2s (loopback audio working)
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+2
-4
@@ -42,11 +42,9 @@ reg ws_int = 0; //internal word select wire
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reg signed [d_width-1: 0] l_data_rx_int = 'sb0; //internal left channel rx data buffer
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reg signed [d_width-1: 0] r_data_rx_int = 'sb0; //internal right channel rx data buffer
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reg signed [d_width-1: 0] reg_r_data_rx = 'sb0;
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reg signed [d_width-1: 0] reg_l_data_rx = 'sb0;
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reg [2: 0] sclk_cnt = 0; //counter of master clocks during half period of serial clock
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reg [3: 0] sclk_cnt = 0; //counter of master clocks during half period of serial clock
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reg [7: 0] ws_cnt = 0; //counter of serial clock toggles during half period of word select
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@@ -61,7 +59,7 @@ always@(posedge mclk, posedge reset_n) begin
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l_data_rx_int <= 'sb0; //clear internal left channel rx data buffer
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r_data_rx_int <= 'sb0; //clear internal right channel rx data buffer
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end
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else begin //master clock rising edge
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else begin //master clock rising edge
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if (sclk_cnt < mclk_sclk_ratio/2-1) begin //less than half period of sclk
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sclk_cnt <= sclk_cnt + 1; //increment mclk/sclk counter
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end
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