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add flipflop module

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This commit is contained in:
Imants Pulkstenis
2019-11-24 19:27:46 +02:00
parent 5e318949b6
commit 518bbe43cb
3 changed files with 61 additions and 18 deletions
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d_flip-flop.v
+14
View File
@@ -0,0 +1,14 @@
module d_flipflop_sync_rst(
input D,
output reg Q,
input clk,
input reset);
always@(posedge clk, posedge reset)
begin
if(reset)
Q <= 1'd0;
else
Q <= D;
end
endmodule
io_module.v
+10 -10
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@@ -3,7 +3,7 @@ module io_module #( parameter
mclk_sclk_ratio = 4, // number of mclk periods per sclk period mclk_sclk_ratio = 4, // number of mclk periods per sclk period
d_width = 24 // data width d_width = 24 // data width
)( )(
output reset_n, //asynchronous active low reset //output reset, //asynchronous active low reset
input mclk, //master clock input mclk, //master clock
output ad_sclk, //serial clock (or bit clock) output ad_sclk, //serial clock (or bit clock)
output ad_ws, //word select (or left-right clock) output ad_ws, //word select (or left-right clock)
@@ -18,7 +18,7 @@ module io_module #( parameter
output signed [d_width-1: 0] l_data_rx, //left channel data received output signed [d_width-1: 0] l_data_rx, //left channel data received
output signed [d_width-1: 0] r_data_rx, //right channel data received output signed [d_width-1: 0] r_data_rx, //right channel data received
input btnC, input reset,
// // inputs to logic analyzer // // inputs to logic analyzer
// input ch0, // input ch0,
@@ -41,7 +41,7 @@ i2s_sender #(
.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period .sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
.d_width(d_width) //data width .d_width(d_width) //data width
) i2s_sender ( ) i2s_sender (
.reset_n(reset_n), //asynchronous active high reset .reset_n(reset), //asynchronous active high reset
.mclk(mclk), //master clock .mclk(mclk), //master clock
.sclk(da_sclk), //serial clock (or bit clock) .sclk(da_sclk), //serial clock (or bit clock)
.ws(da_ws), //word select (or left-right clock) .ws(da_ws), //word select (or left-right clock)
@@ -57,7 +57,7 @@ i2s_receicer #(
.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period .sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
.d_width(d_width) //data width .d_width(d_width) //data width
) i2s_receicer ( ) i2s_receicer (
.reset_n(reset_n), //asynchronous active high reset .reset_n(reset), //asynchronous active high reset
.mclk(mclk), //master clock .mclk(mclk), //master clock
.sclk(ad_sclk), //serial clock (or bit clock) .sclk(ad_sclk), //serial clock (or bit clock)
.ws(ad_ws), //word select (or left-right clock) .ws(ad_ws), //word select (or left-right clock)
@@ -80,11 +80,11 @@ JXADC_controler JXADC_controler(
.JXADC(JXADC) // output for logic analizer .JXADC(JXADC) // output for logic analizer
); );
// debounce reset button // // debounce reset button
debounce_switch debounce_switch_reset( // debounce_switch debounce_switch_reset(
.clk(mclk), // .clk(mclk),
.i_switch(btnC), // .i_switch(btnC),
.o_switch(reset_n) // .o_switch(reset_n)
); // );
endmodule endmodule
top.v
+35 -6
View File
@@ -33,7 +33,9 @@ wire master_clk; // 11.29 MHz master clock
wire clk_25MHz; // wire clk_25MHz; //
wire reset_n; wire w_reset, w_reset1, w_reset2, w_reset3,
w_reset4, w_reset5;
wire [d_width-1: 0] r_data_tx; wire [d_width-1: 0] r_data_tx;
wire [d_width-1: 0] l_data_tx; wire [d_width-1: 0] l_data_tx;
wire [d_width-1: 0] r_data_rx; wire [d_width-1: 0] r_data_rx;
@@ -47,22 +49,49 @@ wire w_dv_from_eff;
wire w_rd_en_from_eff; wire w_rd_en_from_eff;
wire w_internal_reset;
//-----sub modules-------------------------- //-----sub modules--------------------------
// declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S // declare PLL to create 11.29 MHz master clock from 100 MHz system clock for I2S
//
// Common clocking errors with 7-Series FPGAs
// http://www.markharvey.info/art/7clk_19.10.2015/7clk_19.10.2015.html
clk_wiz_0 m_clk( clk_wiz_0 m_clk(
.clk_in1(clk), .clk_in1(clk),
.clk_out1(master_clk), // 11.29 MHz master clock for I2S .clk_out1(master_clk), // 11.29 MHz master clock for I2S
.clk_out2(clk_25MHz) // 25MHz main clock .clk_out2(clk_25MHz), // 25MHz main clock
.locked(w_internal_reset),
.reset(btnC)
); );
// Flip-flops for reset
d_flipflop_sync_rst D_flipflop1 (
.D(1'b0),
.Q(w_reset1),
.clk(master_clk),
.reset(~w_internal_reset));
d_flipflop_sync_rst D_flipflop2 (
.D(w_reset1),
.Q(w_reset2),
.clk(master_clk),
.reset(~w_internal_reset));
d_flipflop_sync_rst D_flipflop3 (
.D(w_reset2),
.Q(w_reset),
.clk(master_clk),
.reset(~w_internal_reset));
io_module #( io_module #(
.mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period .mclk_sclk_ratio(mclk_sclk_ratio), //number of mclk periods per sclk period
.sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period .sclk_ws_ratio(sclk_ws_ratio), //number of sclk periods per word select period
.d_width(d_width) //data width .d_width(d_width) //data width
) io_module ( ) io_module (
.reset_n(reset_n), //asynchronous active high reset //.reset_n(reset_n), //asynchronous active high reset
.mclk(master_clk), //master clock .mclk(master_clk), //master clock
.da_sclk(da_sclk), //serial clock (or bit clock) .da_sclk(da_sclk), //serial clock (or bit clock)
.da_ws(da_lrck), //word select (or left-right clock) .da_ws(da_lrck), //word select (or left-right clock)
@@ -73,7 +102,7 @@ io_module #(
.l_data_tx(l_data_tx), //left channel data to transmit .l_data_tx(l_data_tx), //left channel data to transmit
.r_data_tx(r_data_tx), //right channel data to transmit .r_data_tx(r_data_tx), //right channel data to transmit
.btnC(btnC), //reset button input .reset(w_reset), //reset
.l_data_rx(l_data_rx), //left channel data received .l_data_rx(l_data_rx), //left channel data received
.r_data_rx(r_data_rx), //right channel data received .r_data_rx(r_data_rx), //right channel data received
@@ -98,7 +127,7 @@ effect_controler #(
.d_width(d_width), // data width .d_width(d_width), // data width
.memory_d_width(memory_d_width) .memory_d_width(memory_d_width)
) effect_controler ( ) effect_controler (
.reset(reset_n), // asynchronous active high reset .reset(w_reset), // asynchronous active high reset
.mclk(master_clk), .mclk(master_clk),
.clk(clk_25MHz), .clk(clk_25MHz),
.i_l_data(l_data_rx), // left channel data received .i_l_data(l_data_rx), // left channel data received
@@ -120,7 +149,7 @@ effect_module #(
.d_width(memory_d_width) // data width .d_width(memory_d_width) // data width
) effect_module ( ) effect_module (
.clk(clk_25MHz), .clk(clk_25MHz),
.reset(reset_n), .reset(w_reset),
.sw(sw), // effect control swiches .sw(sw), // effect control swiches
.i_data_ready(w_dv_to_eff), // data ready to read .i_data_ready(w_dv_to_eff), // data ready to read
.i_data(w_data_to_eff), // data input form effect controler .i_data(w_data_to_eff), // data input form effect controler