30 lines
496 B
Verilog
30 lines
496 B
Verilog
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - SR latch module for counter
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//
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// Detailed module description:
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//
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// This is Flip Flop for START/STOP function
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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module flip_flop (
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input start,
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output out);
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reg r_out = 1'b0;
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always@(posedge start) begin
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r_out <= ~r_out;
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end
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assign out = r_out;
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endmodule |