60 lines
1.0 KiB
Verilog
60 lines
1.0 KiB
Verilog
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - Testbench for 7-segment module
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//
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// Detailed module description:
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//
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// This module inputs slowly incrementing
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// numbers in 7-segment module
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//
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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`include "7segment.v"
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module bin_7segment_tb();
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reg clk = 1'b0;
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reg [15:0] in = 'b0;
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wire [6:0] seg;
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wire [3:0] an;
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wire dp;
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always #1 clk <= ~clk;
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always #40 in <= in + 1;
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initial
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begin
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#1000;
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$finish();
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end
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initial
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begin
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$display(" ");
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$display("----------------------------------------------");
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$display(" Starting Testbench...");
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$dumpfile("wave.vcd");
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$dumpvars(0);
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$display("----------------------------------------------");
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$display(" ");
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end
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bin_7segment test_unit1(
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.clk(clk),
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.in(in),
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.seg(seg),
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.an(an),
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.dp(dp)
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);
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endmodule |