151 lines
4.8 KiB
Verilog
151 lines
4.8 KiB
Verilog
/////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - bin_7segment module for counter
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//
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// Detailed module description:
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//
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// This module 16bit input transforms
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// in 7-segment display induvidual segments
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// as outputs. Input clock is 10kHz and it
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// drives common anode for 7-segment display
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//
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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module bin_7segment(
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input clk, // clock working with 10kHz
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input [15:0] in, // input
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output [6:0] seg, // individual segments of number
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output [3:0] an, // anode to select character
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output dp // dot on 7segment display
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);
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//-------------Internal Constants---------------------------
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parameter SIZE = 2;
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parameter [SIZE-1:0] ONE = 2'b00,
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TWO = 2'b01,
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THREE = 2'b10,
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FOUR = 2'b11;
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reg [SIZE-1:0] state=ONE, next=TWO;
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reg [3:0] nibble = 'b0 ;
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//---------State register sequential always block-----------
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always @(posedge clk ) begin
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state <= next;
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end
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//----Next state & outputs, combinational always block------
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always@(posedge clk)begin
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case(state)
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ONE : begin
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next <= TWO;
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nibble <= in[3:0];
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end
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TWO : begin
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next <= THREE;
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nibble <= in[7:4];
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end
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THREE : begin
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next <= FOUR;
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nibble <= in[11:8];
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end
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FOUR : begin
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next <= ONE;
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nibble <= in[15:12];
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end
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endcase
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end
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assign seg[6] = ( nibble == 4'h2 ||
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nibble == 4'h3 ||
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nibble == 4'h4 ||
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nibble == 4'h5 ||
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nibble == 4'h6 ||
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nibble == 4'h8 ||
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nibble == 4'h9 ||
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nibble == 4'hA ||
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nibble == 4'hB ||
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nibble == 4'hD ||
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nibble == 4'hE ||
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nibble == 4'hF ) ? 1'b0 : 1'b1;
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assign seg[5] = ( nibble == 4'h0 ||
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nibble == 4'h4 ||
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nibble == 4'h5 ||
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nibble == 4'h6 ||
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nibble == 4'h8 ||
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nibble == 4'h9 ||
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nibble == 4'hA ||
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nibble == 4'hB ||
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nibble == 4'hC ||
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nibble == 4'hE ||
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nibble == 4'hF ) ? 1'b0 : 1'b1;
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assign seg[4] = ( nibble == 4'h0 ||
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nibble == 4'h2 ||
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nibble == 4'h6 ||
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nibble == 4'h8 ||
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nibble == 4'hA ||
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nibble == 4'hB ||
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nibble == 4'hC ||
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nibble == 4'hD ||
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nibble == 4'hE ||
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nibble == 4'hF ) ? 1'b0 : 1'b1;
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assign seg[3] = ( nibble == 4'h0 ||
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nibble == 4'h2 ||
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nibble == 4'h3 ||
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nibble == 4'h5 ||
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nibble == 4'h6 ||
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nibble == 4'h8 ||
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nibble == 4'h9 ||
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nibble == 4'hB ||
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nibble == 4'hC ||
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nibble == 4'hD ||
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nibble == 4'hE ) ? 1'b0 : 1'b1;
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assign seg[2] = ( nibble == 4'h0 ||
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nibble == 4'h1 ||
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nibble == 4'h3 ||
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nibble == 4'h4 ||
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nibble == 4'h5 ||
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nibble == 4'h6 ||
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nibble == 4'h7 ||
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nibble == 4'h8 ||
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nibble == 4'h9 ||
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nibble == 4'hA ||
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nibble == 4'hB ||
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nibble == 4'hD ) ? 1'b0 : 1'b1;
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assign seg[1] = ( nibble == 4'h0 ||
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nibble == 4'h1 ||
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nibble == 4'h2 ||
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nibble == 4'h3 ||
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nibble == 4'h4 ||
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nibble == 4'h7 ||
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nibble == 4'h8 ||
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nibble == 4'h9 ||
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nibble == 4'hA ||
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nibble == 4'hD ) ? 1'b0 : 1'b1;
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assign seg[0] = ( nibble == 4'h0 ||
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nibble == 4'h2 ||
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nibble == 4'h3 ||
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nibble == 4'h5 ||
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nibble == 4'h6 ||
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nibble == 4'h7 ||
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nibble == 4'h8 ||
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nibble == 4'h9 ||
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nibble == 4'hA ||
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nibble == 4'hC ||
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nibble == 4'hE ||
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nibble == 4'hF) ? 1'b0 : 1'b1;
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assign dp = 1'b1; //dot
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assign an[0] = (state==ONE) ? 1'b0 : 1'b1;
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assign an[1] = (state==TWO) ? 1'b0 : 1'b1;
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assign an[2] = (state==THREE) ? 1'b0 : 1'b1;
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assign an[3] = (state==FOUR) ? 1'b0 : 1'b1;
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endmodule |