232 lines
8.3 KiB
VHDL
232 lines
8.3 KiB
VHDL
-- -------------------------------------------------------------
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--
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-- File Name: C:\Users\Imants\Desktop\sin_gen\iir_hdl\ld3_fixed_point2\IIR.vhd
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-- Created: 2020-06-10 11:45:07
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--
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-- Generated by MATLAB 9.3 and HDL Coder 3.11
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--
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--
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-- -------------------------------------------------------------
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-- Rate and Clocking Details
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-- -------------------------------------------------------------
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-- Model base rate: 4.53515e-05
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-- Target subsystem base rate: 4.53515e-05
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--
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--
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-- Clock Enable Sample Time
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-- -------------------------------------------------------------
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-- ce_out 4.53515e-05
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-- -------------------------------------------------------------
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--
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--
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-- Output Signal Clock Enable Sample Time
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-- -------------------------------------------------------------
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-- Out1 ce_out 4.53515e-05
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-- -------------------------------------------------------------
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--
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-- -------------------------------------------------------------
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-- -------------------------------------------------------------
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--
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-- Module: IIR
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-- Source Path: ld3_fixed_point2/IIR
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-- Hierarchy Level: 0
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--
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-- -------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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ENTITY IIR IS
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PORT( clk : IN std_logic;
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reset : IN std_logic;
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clk_enable : IN std_logic;
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In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
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ce_out : OUT std_logic;
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Out1 : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
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);
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END IIR;
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ARCHITECTURE rtl OF IIR IS
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-- Signals
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SIGNAL enb : std_logic;
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SIGNAL enb_const_rate : std_logic;
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SIGNAL Constant_out1 : unsigned(15 DOWNTO 0); -- ufix16_En21
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SIGNAL Constant_out1_1 : unsigned(15 DOWNTO 0); -- ufix16_En21
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SIGNAL In1_signed : signed(15 DOWNTO 0); -- sfix16_En14
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SIGNAL Constant3_out1 : signed(15 DOWNTO 0); -- sfix16_En14
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SIGNAL Constant2_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
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SIGNAL Subtract1_out1 : signed(15 DOWNTO 0); -- sfix16_En9
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SIGNAL Delay1_out1 : signed(15 DOWNTO 0); -- sfix16_En9
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SIGNAL a_3_cast : signed(16 DOWNTO 0); -- sfix17_En16
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SIGNAL a_3_mul_temp : signed(32 DOWNTO 0); -- sfix33_En25
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SIGNAL a_3_cast_1 : signed(31 DOWNTO 0); -- sfix32_En25
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SIGNAL a_3_out1 : signed(15 DOWNTO 0); -- sfix16_En10
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SIGNAL a_2_mul_temp : signed(31 DOWNTO 0); -- sfix32_En23
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SIGNAL a_2_out1 : signed(15 DOWNTO 0); -- sfix16_En9
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SIGNAL Subtract2_sub_cast : signed(31 DOWNTO 0); -- sfix32_En14
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SIGNAL Subtract2_sub_cast_1 : signed(31 DOWNTO 0); -- sfix32_En14
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SIGNAL Subtract2_sub_temp : signed(31 DOWNTO 0); -- sfix32_En14
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SIGNAL Subtract2_out1 : signed(15 DOWNTO 0); -- sfix16_En9
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SIGNAL Subtract1_sub_cast : signed(31 DOWNTO 0); -- sfix32_En10
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SIGNAL Subtract1_sub_cast_1 : signed(31 DOWNTO 0); -- sfix32_En10
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SIGNAL Subtract1_sub_temp : signed(31 DOWNTO 0); -- sfix32_En10
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SIGNAL Subtract1_out1_1 : signed(15 DOWNTO 0); -- sfix16_En9
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SIGNAL b_1_cast : signed(16 DOWNTO 0); -- sfix17_En21
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SIGNAL b_1_mul_temp : signed(32 DOWNTO 0); -- sfix33_En30
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SIGNAL b_1_cast_1 : signed(31 DOWNTO 0); -- sfix32_En30
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SIGNAL b_1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
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SIGNAL b_1_out1_1 : signed(15 DOWNTO 0); -- sfix16_En15
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SIGNAL Constant1_out1 : signed(15 DOWNTO 0); -- sfix16_En20
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SIGNAL Constant1_out1_1 : signed(15 DOWNTO 0); -- sfix16_En20
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SIGNAL Delay1_out1_1 : signed(15 DOWNTO 0); -- sfix16_En9
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SIGNAL b_3_mul_temp : signed(31 DOWNTO 0); -- sfix32_En29
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SIGNAL b_3_out1 : signed(15 DOWNTO 0); -- sfix16_En15
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SIGNAL b_3_out1_1 : signed(15 DOWNTO 0); -- sfix16_En15
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SIGNAL Sum1_add_cast : signed(31 DOWNTO 0); -- sfix32_En15
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SIGNAL Sum1_add_cast_1 : signed(31 DOWNTO 0); -- sfix32_En15
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SIGNAL Sum1_add_temp : signed(31 DOWNTO 0); -- sfix32_En15
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SIGNAL Sum1_out1 : signed(15 DOWNTO 0); -- sfix16_En14
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ATTRIBUTE multstyle : string;
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BEGIN
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Constant_out1 <= to_unsigned(16#D9E8#, 16);
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enb_const_rate <= clk_enable;
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HwModeRegister_process : PROCESS (clk, reset)
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BEGIN
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IF reset = '1' THEN
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Constant_out1_1 <= to_unsigned(16#0000#, 16);
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ELSIF clk'EVENT AND clk = '1' THEN
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IF enb_const_rate = '1' THEN
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Constant_out1_1 <= Constant_out1;
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END IF;
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END IF;
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END PROCESS HwModeRegister_process;
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In1_signed <= signed(In1);
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Constant3_out1 <= to_signed(-16#5E65#, 16);
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Constant2_out1 <= to_unsigned(16#F268#, 16);
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enb <= clk_enable;
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Delay1_process : PROCESS (clk, reset)
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BEGIN
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IF reset = '1' THEN
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Delay1_out1 <= to_signed(16#0000#, 16);
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ELSIF clk'EVENT AND clk = '1' THEN
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IF enb = '1' THEN
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Delay1_out1 <= Subtract1_out1;
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END IF;
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END IF;
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END PROCESS Delay1_process;
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a_3_cast <= signed(resize(Constant2_out1, 17));
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a_3_mul_temp <= a_3_cast * Delay1_out1;
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a_3_cast_1 <= a_3_mul_temp(31 DOWNTO 0);
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a_3_out1 <= a_3_cast_1(30 DOWNTO 15);
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a_2_mul_temp <= Constant3_out1 * Subtract1_out1;
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a_2_out1 <= a_2_mul_temp(29 DOWNTO 14);
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Subtract2_sub_cast <= resize(In1_signed, 32);
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Subtract2_sub_cast_1 <= resize(a_2_out1 & '0' & '0' & '0' & '0' & '0', 32);
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Subtract2_sub_temp <= Subtract2_sub_cast - Subtract2_sub_cast_1;
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Subtract2_out1 <= Subtract2_sub_temp(20 DOWNTO 5);
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Subtract1_sub_cast <= resize(Subtract2_out1 & '0', 32);
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Subtract1_sub_cast_1 <= resize(a_3_out1, 32);
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Subtract1_sub_temp <= Subtract1_sub_cast - Subtract1_sub_cast_1;
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Subtract1_out1_1 <= Subtract1_sub_temp(16 DOWNTO 1);
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reduced_process : PROCESS (clk, reset)
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BEGIN
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IF reset = '1' THEN
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Subtract1_out1 <= to_signed(16#0000#, 16);
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ELSIF clk'EVENT AND clk = '1' THEN
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IF enb = '1' THEN
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Subtract1_out1 <= Subtract1_out1_1;
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END IF;
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END IF;
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END PROCESS reduced_process;
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b_1_cast <= signed(resize(Constant_out1_1, 17));
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b_1_mul_temp <= b_1_cast * Subtract1_out1;
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b_1_cast_1 <= b_1_mul_temp(31 DOWNTO 0);
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b_1_out1 <= b_1_cast_1(30 DOWNTO 15);
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PipelineRegister_process : PROCESS (clk, reset)
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BEGIN
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IF reset = '1' THEN
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b_1_out1_1 <= to_signed(16#0000#, 16);
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ELSIF clk'EVENT AND clk = '1' THEN
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IF enb_const_rate = '1' THEN
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b_1_out1_1 <= b_1_out1;
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END IF;
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END IF;
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END PROCESS PipelineRegister_process;
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Constant1_out1 <= to_signed(-16#6CF4#, 16);
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HwModeRegister2_process : PROCESS (clk, reset)
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BEGIN
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IF reset = '1' THEN
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Constant1_out1_1 <= to_signed(16#0000#, 16);
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ELSIF clk'EVENT AND clk = '1' THEN
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IF enb_const_rate = '1' THEN
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Constant1_out1_1 <= Constant1_out1;
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END IF;
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END IF;
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END PROCESS HwModeRegister2_process;
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HwModeRegister3_process : PROCESS (clk, reset)
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BEGIN
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IF reset = '1' THEN
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Delay1_out1_1 <= to_signed(16#0000#, 16);
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ELSIF clk'EVENT AND clk = '1' THEN
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IF enb = '1' THEN
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Delay1_out1_1 <= Delay1_out1;
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END IF;
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END IF;
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END PROCESS HwModeRegister3_process;
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b_3_mul_temp <= Constant1_out1_1 * Delay1_out1_1;
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b_3_out1 <= b_3_mul_temp(29 DOWNTO 14);
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PipelineRegister1_process : PROCESS (clk, reset)
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BEGIN
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IF reset = '1' THEN
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b_3_out1_1 <= to_signed(16#0000#, 16);
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ELSIF clk'EVENT AND clk = '1' THEN
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IF enb = '1' THEN
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b_3_out1_1 <= b_3_out1;
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END IF;
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END IF;
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END PROCESS PipelineRegister1_process;
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Sum1_add_cast <= resize(b_1_out1_1, 32);
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Sum1_add_cast_1 <= resize(b_3_out1_1, 32);
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Sum1_add_temp <= Sum1_add_cast + Sum1_add_cast_1;
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Sum1_out1 <= Sum1_add_temp(16 DOWNTO 1);
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Out1 <= std_logic_vector(Sum1_out1);
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ce_out <= clk_enable;
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END rtl;
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