622 lines
12 KiB
VHDL
622 lines
12 KiB
VHDL
-----------------------------
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-- Author - Imants Pulkstenis
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-- Date - 04.06.2020
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-- Project name - Lab work No3
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-- Module name - sin_gen
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--
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-- Detailed module description:
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-- DDS sinusoidal signal generator
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity sin_gen is
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generic
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(
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phase_width : integer := 9;
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data_width : integer := 16;
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sampling_f : integer := 4535; -- 100MHz/22050
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clock_cnt_width : integer := 13
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);
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port
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(
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clk : in std_logic; --100mhz clock
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rst : in std_logic; --rst
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phase_incr : in std_Logic_vector(phase_width - 1 downto 0); --"frequency"
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phase_out : out std_Logic_vector(phase_width - 1 downto 0);
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signal_out : out std_Logic_vector(data_width - 1 downto 0);
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fs_out : out std_logic --output sampling clock for debuging
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);
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end sin_gen;
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--define inside of the module
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architecture behavioral of sin_gen is
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--define inside use signals
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type rom_table is array ( 0 to 2**phase_width - 1) of std_logic_vector(data_width - 1 downto 0);
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constant signal_rom_table : rom_table :=
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(
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0 => x"0000",
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1 => x"00c9",
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2 => x"0192",
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3 => x"025b",
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4 => x"0324",
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5 => x"03ed",
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6 => x"04b5",
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7 => x"057e",
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8 => x"0646",
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9 => x"070e",
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10 => x"07d6",
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11 => x"089d",
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12 => x"0964",
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13 => x"0a2b",
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14 => x"0af1",
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15 => x"0bb7",
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16 => x"0c7c",
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17 => x"0d41",
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18 => x"0e06",
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19 => x"0eca",
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20 => x"0f8d",
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21 => x"1050",
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22 => x"1112",
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23 => x"11d3",
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24 => x"1294",
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25 => x"1354",
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26 => x"1413",
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27 => x"14d2",
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28 => x"1590",
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29 => x"164d",
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30 => x"1709",
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31 => x"17c4",
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32 => x"187e",
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33 => x"1937",
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34 => x"19f0",
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35 => x"1aa7",
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36 => x"1b5d",
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37 => x"1c12",
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38 => x"1cc7",
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39 => x"1d7a",
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40 => x"1e2b",
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41 => x"1edc",
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42 => x"1f8c",
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43 => x"203a",
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44 => x"20e7",
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45 => x"2193",
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46 => x"223e",
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47 => x"22e7",
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48 => x"238f",
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49 => x"2435",
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50 => x"24da",
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51 => x"257e",
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52 => x"2620",
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53 => x"26c1",
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54 => x"2760",
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55 => x"27fe",
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56 => x"289a",
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57 => x"2935",
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58 => x"29ce",
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59 => x"2a65",
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60 => x"2afb",
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61 => x"2b8f",
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62 => x"2c22",
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63 => x"2cb2",
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64 => x"2d41",
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65 => x"2dcf",
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66 => x"2e5a",
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67 => x"2ee4",
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68 => x"2f6c",
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69 => x"2ff2",
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70 => x"3076",
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71 => x"30f9",
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72 => x"3179",
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73 => x"31f8",
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74 => x"3274",
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75 => x"32ef",
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76 => x"3368",
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77 => x"33df",
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78 => x"3453",
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79 => x"34c6",
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80 => x"3537",
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81 => x"35a6",
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82 => x"3612",
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83 => x"367d",
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84 => x"36e5",
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85 => x"374b",
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86 => x"37b0",
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87 => x"3812",
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88 => x"3872",
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89 => x"38cf",
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90 => x"392b",
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91 => x"3984",
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92 => x"39db",
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93 => x"3a30",
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94 => x"3a83",
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95 => x"3ad3",
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96 => x"3b21",
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97 => x"3b6d",
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98 => x"3bb6",
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99 => x"3bfd",
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100 => x"3c42",
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101 => x"3c85",
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102 => x"3cc5",
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103 => x"3d03",
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104 => x"3d3f",
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105 => x"3d78",
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106 => x"3daf",
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107 => x"3de3",
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108 => x"3e15",
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109 => x"3e45",
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110 => x"3e72",
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111 => x"3e9d",
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112 => x"3ec5",
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113 => x"3eeb",
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114 => x"3f0f",
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115 => x"3f30",
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116 => x"3f4f",
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117 => x"3f6b",
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118 => x"3f85",
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119 => x"3f9c",
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120 => x"3fb1",
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121 => x"3fc4",
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122 => x"3fd4",
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123 => x"3fe1",
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124 => x"3fec",
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125 => x"3ff5",
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126 => x"3ffb",
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127 => x"3fff",
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128 => x"4000",
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129 => x"3fff",
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130 => x"3ffb",
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131 => x"3ff5",
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132 => x"3fec",
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133 => x"3fe1",
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134 => x"3fd4",
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135 => x"3fc4",
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136 => x"3fb1",
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137 => x"3f9c",
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138 => x"3f85",
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139 => x"3f6b",
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140 => x"3f4f",
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141 => x"3f30",
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142 => x"3f0f",
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143 => x"3eeb",
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144 => x"3ec5",
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145 => x"3e9d",
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146 => x"3e72",
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147 => x"3e45",
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148 => x"3e15",
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149 => x"3de3",
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150 => x"3daf",
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151 => x"3d78",
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152 => x"3d3f",
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153 => x"3d03",
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154 => x"3cc5",
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155 => x"3c85",
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156 => x"3c42",
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157 => x"3bfd",
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158 => x"3bb6",
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159 => x"3b6d",
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160 => x"3b21",
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161 => x"3ad3",
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162 => x"3a83",
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163 => x"3a30",
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164 => x"39db",
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165 => x"3984",
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166 => x"392b",
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167 => x"38cf",
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168 => x"3872",
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169 => x"3812",
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170 => x"37b0",
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171 => x"374b",
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172 => x"36e5",
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173 => x"367d",
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174 => x"3612",
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175 => x"35a6",
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176 => x"3537",
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177 => x"34c6",
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178 => x"3453",
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179 => x"33df",
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180 => x"3368",
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181 => x"32ef",
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182 => x"3274",
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183 => x"31f8",
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184 => x"3179",
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185 => x"30f9",
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186 => x"3076",
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187 => x"2ff2",
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188 => x"2f6c",
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189 => x"2ee4",
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190 => x"2e5a",
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191 => x"2dcf",
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192 => x"2d41",
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193 => x"2cb2",
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194 => x"2c22",
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195 => x"2b8f",
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196 => x"2afb",
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197 => x"2a65",
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198 => x"29ce",
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199 => x"2935",
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200 => x"289a",
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201 => x"27fe",
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202 => x"2760",
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203 => x"26c1",
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204 => x"2620",
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205 => x"257e",
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206 => x"24da",
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207 => x"2435",
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208 => x"238f",
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209 => x"22e7",
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210 => x"223e",
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211 => x"2193",
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212 => x"20e7",
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213 => x"203a",
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214 => x"1f8c",
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215 => x"1edc",
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216 => x"1e2b",
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217 => x"1d7a",
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218 => x"1cc7",
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219 => x"1c12",
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220 => x"1b5d",
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221 => x"1aa7",
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222 => x"19f0",
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223 => x"1937",
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224 => x"187e",
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225 => x"17c4",
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226 => x"1709",
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227 => x"164d",
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228 => x"1590",
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229 => x"14d2",
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230 => x"1413",
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231 => x"1354",
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232 => x"1294",
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233 => x"11d3",
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234 => x"1112",
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235 => x"1050",
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236 => x"0f8d",
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237 => x"0eca",
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238 => x"0e06",
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239 => x"0d41",
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240 => x"0c7c",
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241 => x"0bb7",
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242 => x"0af1",
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243 => x"0a2b",
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244 => x"0964",
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245 => x"089d",
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246 => x"07d6",
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247 => x"070e",
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248 => x"0646",
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249 => x"057e",
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250 => x"04b5",
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251 => x"03ed",
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252 => x"0324",
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253 => x"025b",
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254 => x"0192",
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255 => x"00c9",
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256 => x"0000",
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257 => x"ff37",
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258 => x"fe6e",
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259 => x"fda5",
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260 => x"fcdc",
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261 => x"fc13",
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262 => x"fb4b",
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263 => x"fa82",
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264 => x"f9ba",
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265 => x"f8f2",
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266 => x"f82b",
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267 => x"f763",
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268 => x"f69c",
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269 => x"f5d5",
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270 => x"f50f",
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271 => x"f449",
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272 => x"f384",
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273 => x"f2bf",
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274 => x"f1fa",
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275 => x"f136",
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276 => x"f073",
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277 => x"efb0",
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278 => x"eeee",
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279 => x"ee2d",
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280 => x"ed6c",
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281 => x"ecac",
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282 => x"ebed",
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283 => x"eb2e",
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284 => x"ea71",
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285 => x"e9b4",
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286 => x"e8f8",
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287 => x"e83c",
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288 => x"e782",
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289 => x"e6c9",
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290 => x"e611",
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291 => x"e559",
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292 => x"e4a3",
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293 => x"e3ee",
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294 => x"e33a",
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295 => x"e287",
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296 => x"e1d5",
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297 => x"e124",
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298 => x"e074",
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299 => x"dfc6",
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300 => x"df19",
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301 => x"de6d",
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302 => x"ddc3",
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303 => x"dd1a",
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304 => x"dc72",
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305 => x"dbcb",
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306 => x"db26",
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307 => x"da82",
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308 => x"d9e0",
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309 => x"d93f",
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310 => x"d8a0",
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311 => x"d802",
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312 => x"d766",
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313 => x"d6cc",
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314 => x"d633",
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315 => x"d59b",
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316 => x"d505",
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317 => x"d471",
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318 => x"d3df",
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319 => x"d34e",
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320 => x"d2bf",
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321 => x"d232",
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322 => x"d1a6",
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323 => x"d11c",
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324 => x"d094",
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325 => x"d00e",
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326 => x"cf8a",
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327 => x"cf08",
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328 => x"ce87",
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329 => x"ce09",
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330 => x"cd8c",
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331 => x"cd11",
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332 => x"cc98",
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333 => x"cc22",
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334 => x"cbad",
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335 => x"cb3a",
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336 => x"cac9",
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337 => x"ca5b",
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338 => x"c9ee",
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339 => x"c984",
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340 => x"c91b",
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341 => x"c8b5",
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342 => x"c851",
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343 => x"c7ef",
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344 => x"c78f",
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345 => x"c731",
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346 => x"c6d6",
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347 => x"c67c",
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348 => x"c625",
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349 => x"c5d0",
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350 => x"c57e",
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351 => x"c52d",
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352 => x"c4df",
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353 => x"c493",
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354 => x"c44a",
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355 => x"c403",
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356 => x"c3be",
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357 => x"c37b",
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358 => x"c33b",
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359 => x"c2fd",
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360 => x"c2c2",
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361 => x"c288",
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362 => x"c252",
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363 => x"c21d",
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364 => x"c1eb",
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365 => x"c1bb",
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366 => x"c18e",
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367 => x"c163",
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368 => x"c13b",
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369 => x"c115",
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370 => x"c0f1",
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371 => x"c0d0",
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372 => x"c0b1",
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373 => x"c095",
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374 => x"c07b",
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375 => x"c064",
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376 => x"c04f",
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377 => x"c03d",
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378 => x"c02d",
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379 => x"c01f",
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380 => x"c014",
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381 => x"c00b",
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382 => x"c005",
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383 => x"c001",
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384 => x"c000",
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385 => x"c001",
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386 => x"c005",
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387 => x"c00b",
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388 => x"c014",
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389 => x"c01f",
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390 => x"c02d",
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391 => x"c03d",
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392 => x"c04f",
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393 => x"c064",
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394 => x"c07b",
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395 => x"c095",
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396 => x"c0b1",
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397 => x"c0d0",
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398 => x"c0f1",
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399 => x"c115",
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400 => x"c13b",
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401 => x"c163",
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402 => x"c18e",
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403 => x"c1bb",
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404 => x"c1eb",
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405 => x"c21d",
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406 => x"c252",
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407 => x"c288",
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408 => x"c2c2",
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409 => x"c2fd",
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410 => x"c33b",
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411 => x"c37b",
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412 => x"c3be",
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413 => x"c403",
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414 => x"c44a",
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415 => x"c493",
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416 => x"c4df",
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417 => x"c52d",
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418 => x"c57e",
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419 => x"c5d0",
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420 => x"c625",
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421 => x"c67c",
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422 => x"c6d6",
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423 => x"c731",
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424 => x"c78f",
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425 => x"c7ef",
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426 => x"c851",
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427 => x"c8b5",
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428 => x"c91b",
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429 => x"c984",
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430 => x"c9ee",
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431 => x"ca5b",
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432 => x"cac9",
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433 => x"cb3a",
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434 => x"cbad",
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435 => x"cc22",
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436 => x"cc98",
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437 => x"cd11",
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438 => x"cd8c",
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439 => x"ce09",
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440 => x"ce87",
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441 => x"cf08",
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442 => x"cf8a",
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443 => x"d00e",
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444 => x"d094",
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445 => x"d11c",
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446 => x"d1a6",
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447 => x"d232",
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448 => x"d2bf",
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449 => x"d34e",
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450 => x"d3df",
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451 => x"d471",
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452 => x"d505",
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453 => x"d59b",
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454 => x"d633",
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455 => x"d6cc",
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456 => x"d766",
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457 => x"d802",
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458 => x"d8a0",
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459 => x"d93f",
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460 => x"d9e0",
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461 => x"da82",
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462 => x"db26",
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463 => x"dbcb",
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464 => x"dc72",
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465 => x"dd1a",
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466 => x"ddc3",
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467 => x"de6d",
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468 => x"df19",
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469 => x"dfc6",
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470 => x"e074",
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471 => x"e124",
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472 => x"e1d5",
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473 => x"e287",
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474 => x"e33a",
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|
475 => x"e3ee",
|
|
476 => x"e4a3",
|
|
477 => x"e559",
|
|
478 => x"e611",
|
|
479 => x"e6c9",
|
|
480 => x"e782",
|
|
481 => x"e83c",
|
|
482 => x"e8f8",
|
|
483 => x"e9b4",
|
|
484 => x"ea71",
|
|
485 => x"eb2e",
|
|
486 => x"ebed",
|
|
487 => x"ecac",
|
|
488 => x"ed6c",
|
|
489 => x"ee2d",
|
|
490 => x"eeee",
|
|
491 => x"efb0",
|
|
492 => x"f073",
|
|
493 => x"f136",
|
|
494 => x"f1fa",
|
|
495 => x"f2bf",
|
|
496 => x"f384",
|
|
497 => x"f449",
|
|
498 => x"f50f",
|
|
499 => x"f5d5",
|
|
500 => x"f69c",
|
|
501 => x"f763",
|
|
502 => x"f82b",
|
|
503 => x"f8f2",
|
|
504 => x"f9ba",
|
|
505 => x"fa82",
|
|
506 => x"fb4b",
|
|
507 => x"fc13",
|
|
508 => x"fcdc",
|
|
509 => x"fda5",
|
|
510 => x"fe6e",
|
|
511 => x"ff37"
|
|
);
|
|
|
|
|
|
-- phase counter
|
|
signal phase_cnt : unsigned(phase_width - 1 downto 0) := (others => '0');
|
|
|
|
-- clock divider counter - for generating 22050Hz fs clock
|
|
signal clock_cnt : unsigned(clock_cnt_width - 1 downto 0) := (others => '0');
|
|
-- clock output
|
|
signal clock_out : std_logic := '0';
|
|
|
|
begin --define the operation of the module!
|
|
|
|
--phase output for debugging
|
|
phase_out <= std_logic_Vector(phase_cnt);
|
|
--clcock output for debugiung
|
|
fs_out <= std_logic(clock_out);
|
|
|
|
--phase counter
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if rst = '1' then
|
|
phase_cnt <= (others => '0');
|
|
clock_cnt <= (others => '0');
|
|
else
|
|
if clock_cnt <= sampling_f then
|
|
clock_cnt <= unsigned(clock_cnt) + 1;
|
|
if clock_cnt = (sampling_f-1)/2 then
|
|
clock_out <= not clock_out;
|
|
end if;
|
|
else
|
|
phase_cnt <= unsigned(phase_cnt) + unsigned(phase_incr);
|
|
clock_cnt <= (others => '0');
|
|
clock_out <= not clock_out;
|
|
end if;
|
|
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
|
|
--data output
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
if rst = '1' then
|
|
signal_out <= (others => '0');
|
|
else
|
|
--assign value from table
|
|
signal_out <= signal_rom_table(to_integer(unsigned(phase_cnt)));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
end behavioral;
|
|
|
|
|
|
|
|
|
|
|