58 lines
934 B
VHDL
58 lines
934 B
VHDL
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-- Imants Pulkstenis
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-- 10.02.2020
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-- RTR532 PS1
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-- PS1
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--
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-- Task 2 for Problem set #1 – My first VHDL code
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--
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-- Revision:
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-- A - initial design
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--
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--
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-----------------------------
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--Libraries
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--define entity (module) connections to "outside"
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entity ps01q is
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port
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(
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a : in std_Logic;
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b : in std_logic;
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c : in std_logic;
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y1 : out std_logic;
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y2 : out std_logic
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);
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end ps01q;
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--define inside of the module (internal signals, components and architecture)
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architecture behavioral of ps01q is
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--define inside use signals
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signal SIG_INTERNAL : std_logic;
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begin
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--gate one
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SIG_INTERNAL <= A xor B;
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--gate two
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Y2 <= C xnor SIG_INTERNAL;
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--gate three
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Y1 <= A nor B; -- in assignment gate three is not ?????
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end behavioral;
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