35 lines
642 B
Verilog
35 lines
642 B
Verilog
/////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - SR latch module for counter
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//
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// Detailed module description:
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//
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// This is SR latch for swiching
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// between UP or DOWN counting
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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module sr_latch(
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input wire clk, up, down,
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output wire out
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);
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reg r_out = 1'b0;
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always@(posedge clk) begin
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case ({up,down})
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2'b01 : r_out <= 0;
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2'b10 : r_out <= 1;
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default : r_out <= r_out;
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endcase
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end
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assign out = r_out;
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endmodule
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