29 lines
547 B
Verilog
29 lines
547 B
Verilog
/////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - SR latch module for counter
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//
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// Detailed module description:
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//
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// This is SR latch for swoching
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// between UP or DOWN counting
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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module sr_latch(
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input wire S, R, C,
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output reg Q, notQ
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);
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always@(S, R, C, Q, notQ)
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if(C) begin
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Q <= (~R & Q) | S;
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Q <= (~S & Q) | R;
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end
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endmodule
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