32 lines
552 B
Verilog
32 lines
552 B
Verilog
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - SR latch module for counter
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//
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// Detailed module description:
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//
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// This is Flip Flop for START/STOP function
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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module flip_flop (
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input clk,
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input rst,
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input t,
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output reg q);
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always @ (posedge clk) begin
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if (!rst)
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q <= 0;
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else if (t)
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q <= ~q;
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else
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q <= q;
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end
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endmodule |