67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
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// Author - Imants Pulkstenis
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// Date - 16.02.2020
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// Project name - PS02
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// Module name - Top module for PS02
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//
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// Detailed module description:
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//
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// Includes an existing (my or somebody else’s)
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// design entity (another vhdl or verlilog file)
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// in other design entity
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//
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//
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//
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//
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// Revision:
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// A - initial design
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// B - VHDL code are replaced with Verilog
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//
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/////////////////////////////
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//define connections to outside
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module ps02 #( parameter
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data_width = 32
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)(
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input clk,
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input rst,
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output signed [data_width - 1:0] R,
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output flag
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);
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//define inside of the module
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//define inside use signals
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wire signed [data_width - 1:0] A;
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wire signed [data_width - 1:0] B;
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wire [3:0] op;
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//component declaration for A, B, op signal generator
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//port map for A, B, op signal generator
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ps02_siggen #(
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.data_width(data_width)
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) name_of_unit (
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.clk(clk),
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.rst(rst),
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.A(A),
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.B(B),
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.op(op)
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);
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//component declaration for alu (TASK 1)
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//port map for ALU (TASK 1)
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alu #(
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.data_width(data_width)
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) name_of_alu_unit (
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.clk(clk),
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.A(A),
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.B(B),
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.op(op),
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.R(R),
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.flag(flag)
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);
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endmodule
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