111 lines
1.8 KiB
VHDL
111 lines
1.8 KiB
VHDL
-----------------------------
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-- Author
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-- Date
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-- Project name
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-- Module name
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--
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-- Detailed module description
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--
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--
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-- Revision:
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-- A - initial design
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-- B -
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--
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-----------------------------
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library ieee; --always use this library
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use ieee.std_logic_1164.all; --always use this library
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use ieee.numeric_std.all; --use this library if arithmetic required
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--define connections to outside
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entity fsm_training_traffic is
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port
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(
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clk : in std_logic;
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rst : in std_Logic;
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light : out std_logic_vector(1 downto 0)
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);
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end fsm_training_traffic;
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--define inside of the module
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architecture behavioral of fsm_training_traffic is
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--define inside use signals
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signal state : std_logic_vector(1 downto 0) := "00"; --2b state
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signal cnt : unsigned(7 downto 0) := x"00"; --8b counter
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--define components to use
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begin
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--define the operation of the module!
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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state <= "00";
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cnt <= x"00";
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else
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case state is
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when "00" => --red light 30 secs
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if cnt < 30 then
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cnt <= cnt + 1;
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state <= "00";
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else
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cnt <= 0;
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state <= "01";
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end if;
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when "01" => --yellow light 5 secs
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if cnt < 5 then
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cnt <= cnt + 1;
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state <= "01";
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else
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cnt <= 0;
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state <= "10";
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end if;
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when "10" => --green light 30 secs
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if cnt < 30 then
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cnt <= cnt + 1;
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state <= "10";
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else
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cnt <= 0;
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state <= "11";
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end if;
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when "11" => --yellow light 5 secs
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if cnt < 5 then
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cnt <= cnt + 1;
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state <= "11";
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else
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cnt <= 0;
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state <= "00";
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end if;
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when others =>
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cnt <= 0;
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state <= "00";
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end case;
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end if;
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end if;
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end process;
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light <= "00";
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end behavioral;
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