55 lines
1.2 KiB
Verilog
55 lines
1.2 KiB
Verilog
/////////////////////////////
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// Author - Imants Pulkstenis
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// Date - 24.03.2020
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// Project name - Lab work No2 - Counter
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// Module name - counter module
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//
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// Detailed module description:
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//
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// This module counts form 0000 to ffff
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// in hex
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//
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//
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// Revision:
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// A - initial design
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// B -
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//
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//
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/////////////////////////////
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module counter (
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input clk,
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input reset,
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input enable,
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input direction,
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input [3:0] max,
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output [15:0] counter);
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always@(posedge clk) begin
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if (reset == 'b1) begin
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r_counter <= 'b0;
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end
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else begin
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if(enable)begin
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if (r_adder >= max )begin
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r_adder <= 0;
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if (direction) begin
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r_counter <= r_counter - 1;
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end
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else begin
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r_counter <= r_counter + 1;
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end
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end
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else begin
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r_adder <= r_adder + 1;
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end
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end
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end
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end
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reg [15:0] r_adder = 'b0;
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reg [15:0] r_counter = 'b0;
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assign counter = r_counter;
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endmodule |